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PDF IDT7164S Data sheet ( Hoja de datos )
| Número de pieza | IDT7164S | |
| Descripción | CMOS STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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CMOS Static RAM
64K (8K x 8-Bit)
IDT7164S
IDT7164L
Features
◆ High-speed address/chip select access time
– Military: 20/25/35/45/55/70/85/100ns (max.)
– Industrial: 20/25ns (max.)
– Commercial: 20/25ns (max.)
◆ Low power consumption
◆ Battery backup operation – 2V data retention voltage
(L Version only)
◆ Produced with advanced CMOS high-performance
technology
◆ Inputs and outputs directly TTL-compatible
◆ Three-state outputs
◆ Available in 28-pin DIP, CERDIP and SOJ
◆ Military product compliant to MIL-STD-883, Class B
Description
The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using high-performance, high-reliability CMOS tech-
nology.
Address access times as fast as 20ns are available and the circuit offers
a reduced power standby mode. When CS1 goes HIGH or CS2 goes
LOW, the circuit will automatically go to, and remain in, a low-power stand-
by mode. The low-power (L) version also offers a battery backup data
retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28-
pin 600 mil CERDIP.
Militarygradeproductismanufacturedincompliancewith MIL-STD-
883, Class B, making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
A12
I/O 0
65,536 BIT
MEMORY ARRAY
0
I/O CONTROL
VCC
GND
7
I/O7
CS1
CS2
OE
WE
CONTROL
LOGIC
©2013 Integrated Device Technology, Inc.
1
2967 drw 01
OCTOBER 2013
DSC-2967/16
1 page  
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S20
7164L20
7164S25
7164L25
Symbol
Parameter
Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
20 ____ 25 ____ ns
tAA Address Access Time
____ 19 ____ 25 ns
tACS1(1) Chip Select-1 Access Time
____ 20 ____ 25 ns
tACS2(1) Chip Select-2 Access Time
____ 25 ____ 30 ns
tCLZ1,2(2) Chip Select-1, 2 to Output in Low-Z
5 ____ 5 ____ ns
tOE Output Enable to Output Valid
____ 8 ____ 12 ns
tOLZ(2)
Output Enable to Output in Low-Z
0 ____ 0 ____ ns
tCHZ1,2(2) Chip Select-1,2 to Output in High-Z
____ 9 ____ 13 ns
tOHZ(2)
Output Disable to Output in High-Z
____ 8 ____ 10 ns
tOH Output Hold from Address Change
5 ____ 5 ____ ns
tPU(2) Chip Select to Power Up Time
0 ____ 0 ____ ns
tPD(2) Chip Deselect to Power Down Time
____ 20 ____ 25 ns
Write Cycle
tWC Write Cycle Time
20 ____ 25 ____ ns
tCW1,2
Chip Select to End-of-Write
15 ____ 18 ____ ns
tAW Address Valid to End-of-Write
15 ____ 18 ____ ns
tAS Address Set-up Time
0 ____ 0 ____ ns
tWP Write Pulse Width
tWR1 Write Recovery Time (CS1, WE)
15 ____
0 ____
21 ____ ns
0 ____ ns
tWR2 Write Recovery Time (CS2)
5 ____ 5 ____ ns
tWHZ(2)
Write Enable to Output in High-Z
____ 8 ____ 10 ns
tDW Data to Write Time Overlap
tDH1 Data Hold from Write Time (CS1, WE)
10 ____ 13 ____ ns
0 ____ 0 ____ ns
tDH2 Data Hold from Write Time (CS2)
5 ____ 5 ____ ns
tOW(2)
Output Active from End-of-Write
4 ____ 4 ____ ns
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
2967 tbl 12
6.542
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IDT7164S.PDF ] | |
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