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National Semiconductor - Programmable Timer

Numéro de référence CD4541BM
Description Programmable Timer
Fabricant National Semiconductor 
Logo National Semiconductor 





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CD4541BM fiche technique
February 1988
CD4541BM CD4541BC Programmable Timer
General Description
The CD4541B Programmable Timer is designed with a
16-stage binary counter an integrated oscillator for use with
an external capacitor and two resistors output control logic
and a special power-on reset circuit The special features of
the power-on reset circuit are first no additional static pow-
er consumption and second the part functions across the
full voltage range (3V–15V) whether power-on reset is en-
abled or disabled
Timing and the counter are initialized by turning on power if
the power-on reset is enabled When the power is already
on an external reset pulse will also initialize the timing and
counter After either reset is accomplished the oscillator
frequency is determined by the external RC network The
16-stage counter divides the oscillator frequency by any of 4
digitally controlled division ratios
Features
Y Available division ratios 28 210 213 or 216
Y Increments on positive edge clock transitions
Y Built-in low power RC oscillator (g2% accuracy over
temperature range and g10% supply and g3% over
processing k 10 kHz)
Y Oscillator frequency range DC to 100 kHz
Y Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
Y Automatic reset initializes all counters when power
turns on
Y External master reset totally independent of automatic
reset operation
Y Operates at 2n frequency divider or single transition
timer
Y Q Q select provides output logic level flexibility
Y Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
Y Clock conditioning circuit permits operation with very
slow clock rise and fall times
Y Wide supply voltage range 3 0V to 15V
Y High noise immunity 0 45 VDD (typ )
Y 5V – 10V – 15V parameter ratings
Y Symmetrical output characteristics
Y Maximum input leakage 1 mA at 15V over full tempera-
ture range
Y High output drive (pin 8) min one TTL load
Logic Diagram
VDD e Pin 14
VSS e Pin 7
Connection Diagram
Dual-In-Line Package
TL F 6001 – 1
Order Number CD4541B
N C Not connected
C1995 National Semiconductor Corporation TL F 6001
Top View
TL F 6001 – 2
RRD-B30M105 Printed in U S A

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