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PDF CD4541BC Data sheet ( Hoja de datos )
| Número de pieza | CD4541BC | |
| Descripción | Programmable Timer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CD4541BC (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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October 1987
Revised March 1999
CD4541BC
Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special fea-
tures of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC net-
work. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
Features
s Available division ratios 28, 210, 213, or 216
s Increments on positive edge clock transitions
s Built-in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over pro-
cessing @ < 10 kHz)
s Oscillator frequency range ≈ DC to 100 kHz
s Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
s Automatic reset initializes all counters when power turns
on
s External master reset totally independent of automatic
reset operation
s Operates at 2n frequency divider or single transition
timer
s Q/Q select provides output logic level flexibility
s Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
s Clock conditioning circuit permits operation with very
slow clock rise and fall times
s Wide supply voltage range—3.0V to 15V
s High noise immunity—0.45 VDD (typ.)
s 5V–10V–15V parameter ratings
s Symmetrical output characteristics
s Maximum input leakage 1 µA at 15V over full tempera-
ture range
s High output drive (pin 8) min. one TTL load
Ordering Code:
Order Number Package Number
Package Description
CD4541BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4541BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
N.C.—Not connected
Top View
© 1999 Fairchild Semiconductor Corporation DS006001.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF (refer to test circuits)
Symbol
Parameter
Conditions
Min Typ Max Units
tTLH Output Rise Time
VDD = 5V
50 200
ns
VDD = 10V
30 100
ns
tTHL Output Fall Time
VDD = 15V
VDD = 5V
25 80
50 200
ns
ns
VDD = 10V
30 100
ns
tPLH, tPHL
Turn-Off, Turn-On Propagation Delay,
Clock to Q (28 Output)
VDD = 15V
VDD = 5V
VDD = 10V
25 80
1.8 4.0
0.6 1.5
ns
µs
µs
tPHL, tPLH
Turn-On, Turn-Off Propagation Delay,
Clock to Q (216 Output)
VDD = 15V
VDD = 5V
VDD = 10V
0.4 1.0
3.2 8.0
1.5 3.0
µs
µs
µs
VDD = 15V
1.0 2.0
µs
tWH(CL)
Clock Pulse Width
VDD = 5V
400 200
ns
VDD = 10V
200 100
ns
VDD = 15V
150 70
ns
fCL Clock Pulse Frequency
VDD = 5V
2.5 1.0 MHz
VDD = 10V
6.0 3.0 MHz
VDD = 15V
8.5 4.0 MHz
tWH(R)
MR Pulse Width
VDD = 5V
400 170
ns
VDD = 10V
200 75
ns
VDD = 15V
150 50
ns
CI Average Input Capacitance
Any Input
5.0 7.5
pF
CPD Power Dissipation Capacitance (Note 5)
100 pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note:
AN-90.
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4541BC.PDF ] | |
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