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PDF CD4527BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4527BMS | |
| Descripción | CMOS BCD Rate Multiplier | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4527BMS
December 1992
CMOS BCD Rate Multiplier
Features
Description
• High Voltage Type (20V Rating)
• Cascadable in Multiples of 4-Bits
• Set to “9” Input and “9” Detect Output
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
CD4527BMS is a low power 4-bit digital rate multiplier that
provides an output pulse rate which is the clock input pulse
rate multiplied by 1/10 times the BCD input. For example,
when the BCD input is 8, there will be 8 output pulses for
every 10 input pulses. This device may be used to perform
arithmetic operations (add, subtract, divide, raise to a
power), solve algebraic and differential equations, generate
natural logarithms and trigonometric functions, A/D and D/A
conversion, and frequency division.
For fractional multipliers with more than one digit,
CD4527BMS devices may be cascaded in two different
modes: the Add mode and the Multiply mode (see Figures 9
and 11). In the Add mode,
Output Rate =
(Clock Rate) [0.1BCD1 + 0.01BCD2 + 0.001BCD3 + . . .]
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
In the Multiply mode, the fraction programmed into the first
rate multiplier is multiplied by the fraction programmed into
the second one,
Applications
• Numerical Control
• Instrumentation
• Digital Filtering
• Frequency Synthesis
9 4 36
e.g. x = or 36 output
10 10 100
pulses for every 100 clock input pulses.
The CD4527BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Pinout
CD4527BMS
TOP VIEW
“9” OUT 1
C2
D3
SET TO “9” 4
OUT 5
OUT 6
INHIBIT OUT (CARRY) 7
VSS 8
16 VDD
15 B
14 A
13 CLEAR
12 CASCADE
11 INHIBIT IN (CARRY)
10 STROBE
9 CLOCK
Functional Diagram
CLOCK
INHIBIT 11
(CARRY) IN
SET TO 4
NINE
13
CLEAR
9
÷10
COUNTER
BCD RATE
SELECT INPUTS
A BC D
14 15 2 3
STROBE
10
12 CASCADE
RATE
SELECT
LOGIC
OUT
6
OUT
5
RATE
OUTPUTS
“9” OUT
1
7 INHIBIT
(CARRY) OUT
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1216
File Number 3343
1 page  
Specifications CD4527BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Minimum Clear Removal
Time
TREM VDD = 5V
VDD = 10V
VDD = 15V
Minimum Set Removal
Time
TREM VDD = 5V
VDD = 10V
VDD = 15V
Minimum Set or Clear
Pulse Width
TW VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
CIN Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
MIN
-
-
-
-
-
-
-
-
-
-
MAX
60
40
30
150
80
50
160
90
60
7.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
7-1220
5 Page 
CD4527BMS
Timing Diagram
012345678901234
CLOCK
Qa
Qb
Qc
Qd
R1
R2
R3
R4
OUTPUT (PIN 6)
A ENABLED
B ENABLED
C ENABLED
D ENABLED
INH. OUT
OUTPUT (PIN 6)
PRESET NO. OF 1
PRESET NO. OF 2
PRESET NO. OF 3
PRESET NO. OF 4
PRESET NO. OF 5
PRESET NO. OF 6
PRESET NO. OF 7
PRESET NO. OF 8
PRESET NO. OF 9
FIGURE 11. (SEE LOGIC DIAGRAM)
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1226
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CD4527BMS.PDF ] | |
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