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Intersil Corporation - CMOS Dual 64-Stage Static Shift Register

Numéro de référence CD4517BMS
Description CMOS Dual 64-Stage Static Shift Register
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CD4517BMS fiche technique
CD4517BMS
December 1992
CMOS Dual 64-Stage
Static Shift Register
Features
Description
• High-Voltage Types (20-Volt Rating)
• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V
• Clock Frequency 12MHz (Typ.) at VDD = 10V
• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock
Rise and Fall Times
• Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load, or Two HTL Loads
• 3-State Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V, and 15V Parametric Ratings
• Meets all Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ‘B’ Series CMOS
Devices"
Applications
• Time-delay Circuits
CD4517BMS dual 64-stage static shift
register consists of two independent registers
each having a clock, data, and write enable
input and outputs accessible at taps following
the 16th, 32rd, 48th, and 64th stages. These
taps also serve as input points allowing data
to be inputted at the 17th, 33rd, and 49th
stages when the write enable input is a logic
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
opeation of the CD4517BMS. Inputs at the
intermediate taps allow entry of 64 bits into
the register with 16 clock pulses. The 3-state
outputs permit connection of this device to an
external bus.
The CD4517BMS is supplied in these 16 lead
outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6P
• Scratch-pad Memories
• General-purpose Serial Shift-register Applications
Pinout
CD4517BMS
TOP VIEW
Q16A 1
Q48A 2
WEA 3
CLA 4
Q64A 5
Q32A 6
DA 7
VSS 8
16 VDD
15 Q16B
14 Q48B
13 WEB
12 CLB
11 Q64B
10 Q32B
9 DB
Functional Diagram
CL
CL
Q16
D D1
16 STAGES
CL
Q32
D17
16 STAGES
WE = 0
WE = 1
WE
CL
Q48
D33
16 STAGES
CL
Q64
D49
16 STAGES
STAGE 16
OUT/IN TAP
STAGE32
OUT/IN TAP
STAGE 48
OUT/IN TAP
STAGE 64
OUT/IN TAP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1197
File Number 3341

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