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PDF BL24C16A Data sheet ( Hoja de datos )
| Número de pieza | BL24C16A | |
| Descripción | EEPROM | |
| Fabricantes | BELLING | |
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BL24C02A/04A/08A/16A
Features
Compatible with all I2C bidirectional data
transfer protocol
Memory array:
– 2K bits (256X 8) / 4K bits (512 X 8) / 8K
bits (1024 X 8) / 16K bits (2048 X 8) of
EEPROM
– Page size: 16 bytes
Single supply voltage and high speed:
– 1 MHz
Random and sequential Read modes
Write:
– Byte Write within 3 ms
– Page Write within 3 ms
– Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Enhanced ESD/Latch-up protection
– HBM 8000V
8-lead PDIP/SOP/TSSOP/UDFN and WLCSP4
packages
Description
The BL24C02A/BL24C04A/BL24C08A/BL24C16A
provides 2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-
only memory (EEPROM), organized as
256/512/1024/2048 words of 8 bits each.
The device is optimized for use in many
industrial and commercial applications where
low-power and low-voltage operation are
essential.
Pin Configuration
8-lead PDIP
A0 1
A1 2
A2 3
GND 4
5
6
7
8
VCC A0
WP A1
SCL A2
SDA GND
8-lead SOP
8-lead TSSOP
1 5 VCC A0 1 5
2 6 WP A1 2 6
3
7 SCL A2
3
7
4 8 SDA GND 4 8
8-pad DFN
VCC VCC 1
WP WP 2
SCL SCL 3
SDA SDA 4
5 A0
6 A1
A
7 A2
8 GND B
WLCSP4
12
Vcc Vss
SCL SDA
Bottem view
Marking side
(top view)
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
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BL24C02A/04A/08A/16A
3. Device Addressing
The 2K/4K/8K/16K EEPROM devices all require an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see Figure 5)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant
bits as shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must
compare to their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page
address bit. The two device address bits must compare to their corresponding hardwired input pins.
The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page
addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are
no connect.
The 16K does not use any device address bits but instead the 3 bits are used for memory page
addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most
significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the
chip will return to a standby state.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0"
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (see Figure 6).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are
capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the
first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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BL24C02A/04A/08A/16A
Bus Timing
SCL
tSU.STA
Figure 11. SCL: Serial Clock, SDA: Serial Data I/O
tF
tLOW
tHD.STA
tHIGH
tLOW
tHD.DAT
tSU.DAT
SDA_IN
SDA_OUT
tAA
tDH
Write Cycle Timing
Figure 12. SCL: Serial Clock, SDA: Serial Data I/O
tR
tSU.STO
t BUF
SCL
SDA
Word n
ACK
tWR(1)
STOP
CONDITION
START
CONDITION
Notes:
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited
© 2016 Belling All Rights Reserved www.belling.com.cn
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet BL24C16A.PDF ] | |
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