EDD1232ABBH Datasheet PDF - Elpida Memory
| Part Number | EDD1232ABBH | |
| Description | 128M bits DDR SDRAM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
128M bits DDR SDRAM
EDD1232ABBH (4M words × 32 bits)
Specifications
• Density: 128M bits
• Organization
⎯ 1M words × 32 bits × 4 banks
• Package: 144-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.125V
• Data rate: 400Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge operation for each burst
access
• Driver strength: weak/matched
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/32ms
⎯ Average refresh period: 7.8μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Features
• ×32 organization
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E0874E40 (Ver. 4.0)
Date Published April 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007
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EDD1232ABBH
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
Unit Note
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD,
VDDQ
VSS,
VSSQ
2.375
0
2.5 2.625
00
V1
V
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V2
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V3
Input voltage level,
CK and /CK inputs
VIN (DC)
–0.3
—
VDDQ + 0.3
V4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
—
VDDQ + 0.6
V 5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0874E40 (Ver. 4.0)
5
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