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PDF SEC1210 Data sheet ( Hoja de datos )
| Número de pieza | SEC1210 | |
| Descripción | Smart Card Bridge to USB and UART Interfaces | |
| Fabricantes | Microchip | |
| Logotipo |  |
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SEC1110/SEC1210
Smart Card Bridge to USB and UART Interfaces
General Description
The SEC1110 and SEC1210 provide a single-chip
solution for a Smart Card bridge to USB and UART
interfaces. These bridges are controlled by an
enhanced 8051 micro controller and all chip peripher-
als are accessed and controlled through the SFR or
XDATA register space. TrustSpanTM Technology
enables digital systems to securely communicate, pro-
cess, move and store information on system boards,
across networks and through the cloud.
Feature Highlights
• Smart Card
- The SEC1110 provides one Smart Card inter-
face and the SEC1210 provides two
- Fully compliant with ISO/IEC 7816, EMV 4.2/
4.3, ETSI TS 102 221 and PC/SC standards
- Versatile ETU rate generation, supporting
current and proposed rates (up to 826 Kbps)
- Full support of both T=0 and T=1 protocols
- Full-packet FIFO (261 bytes), for transmit
and receive
- Half-duplex operation (no software interven-
tion required between transmit and receive
phases of exchange)
- Loose real-time response required of soft-
ware (approximately 180 ms)
- Dynamically programmable FIFO threshold
with byte granularity
- Time-out FIFO flush interrupt, independent of
threshold
- Programmable Smart Card clock frequency
- UART-like register file structure
- Supports Class A, Class B, Class C, or Class
AB Smart Cards (1.8 V, 3.0 V and 5.0 V
cards)
- Automatic character repetition for T=0 proto-
col parity error recovery
- Automatic card deactivation on card removal
and on other system events, including per-
sistent parity errors
- Internal procedure byte filtering for T=0 proto-
col
- Protocol timers (Guard, Timeout, and CWT)
for EMV-defined timing parameters
–Detection of an unresponsive card
–Activation/deactivation sequences
–Cold/warm resets
–Monitoring for all EMV timing constraints
–16-bit general purpose down counter for software
timing use
- Fully compliant ESD protection on card pins
• USB
- 12 Mbps USB operation compliant to the
USB 2.0 Specification
- Integrated USB 1.5 K pull-up resistor and
Dp,Dm series termination resistors
- Integrated USB devices controller with:
–8/16/32/64 byte control buffer
–Five 8/16/32/64 byte programmable (bulk/
interrupt) endpoint buffers
• 8051 Processor
- Reduced instruction cycle time (approxi-
mately 9 times 80C51)
- 9.6 MHz max clock speed
- Enhanced peripherals; three 16-bit timers,
watchdog timer, interrupt controller, JTAG
- OTP (One Time Programmable)
ROM : 16 KB RAM : 1.5 KB
• Boot ROM : 16 KB UART (SEC1210 only)
— Standard PC baud rates supported
— 3 M baud high-speed rate (not PC standard)
• SPI (SEC1210 only)
- Master capability with 12 MHz max perfor-
mance
• General
- 5.0 V tolerance on user accessible IO pins
- Self-clocking internal oscillator, no external
crystal required
- 3.6 V - 5.5 V supply input
–Internal 4.8 V comparator disables Class A card
support if the input voltage is too low
- Available in commercial (0ºC to +70ºC) and
industrial (-40ºC to +85ºC) temperature
ranges
Applications
• USB Smart Card reader
• UART-based Smart Card reader
• Dual Smart Card reader
2013 - 2016 Microchip Technology Inc.
DS00001561C-page 1
1 page  
SEC1110/SEC1210
• UART
- Standard PC (9600, 19200, 38400 and 115200) baud rates supported
- 3 M baud high-speed rate (non-PC standard)
• SPI
- Master capability with 12 MHz max performance
• General
- 5.0 V tolerance on user accessible IO pins
- Self-clocking internal oscillator, no external crystal required
- 3.6 V-5.5 V supply input
- Internal 4.8 V comparator disables Class A card support if the input voltage is too low
1.2 Smart Card Subsystem
The SEC1110 and SEC1210 are fully compliant with the prevailing Smart Card standards: ISO7816, EMV, and PC/SC.
It meets and exceeds all existing requirements for communication bit rate (ETU duration) and includes support for pro-
posed bit rates up to 826 Kbps. Signal levels and current limits are also fully compliant.
The Smart Card power is regulated and switched internally, supporting all 5.0 V, 3.0 V, and 1.8 V Smart Cards (classes
A, B, and C, respectively). Over-current protection is provided, and a detected over-current condition is available as an
interrupt. The required standard activation and deactivation sequences are provided with software interaction. However,
deactivation is handled in hardware as the card is being removed. This scenario ensures the required sequence regard-
less of software participation. If the system clock is inactive at the time, the card movement is detected asynchronously,
and the Wake-On Event feature is used to re-start the system clock so that the de-activation sequence can continue.
Interface signals to the Smart Card are designed to meet both standard drive levels and current limitations internally,
requiring no external series resistors. ESD protection on these signals meets the full standard requirements.
The device is a superset of the familiar 16450 UART architecture, with extensions in the form of a larger FIFO, special-
ized state machines for T=0 protocol parsing, automatic half-duplex turnaround at the completion of a transmitted mes-
sage, and a specially-designed set of timers to enforce standards compliance in timing (as required of a terminal by the
ISO7816 and EMV standards).
With the full-packet-depth FIFO on-chip, software is almost totally excluded from real-time requirements. It loads an out-
going message into the FIFO, triggers the transfer, and reads the returned data at any time after it becomes available.
The reset sequence (cold or warm) is equally hands-off: software sets up the sequence and activates the reset, and is
alerted when the ATR message has been received (via the FIFO Threshold Interrupt). The threshold is dynamically pro-
grammable with byte granularity, so that threshold interrupts can be received at various stages in the processing of a
message of initially unknown length (such as ATR).
For detecting data time-outs, and for other mandatory timing tasks having to do with communication with a Smart Card,
a set of three protocol timers is provided:
• Time-out timer, for monitoring the standard WWT, BWT and WTX time-out intervals
• CWT timer, for monitoring the T=1 CWT time-out interval
• Guard timer, for ensuring the BGT and EGT transmission intervals, with special usage during a Reset sequence.
A separate general purpose timer is provided for software driver use.
Synchronous card support using GPIOs controlled via registers in the Smart Card device.
2013 - 2016 Microchip Technology Inc.
DS00001561C-page 5
5 Page 
4.0 PIN CONFIGURATIONS
FIGURE 4-1:
SEC1110 16-PIN QFN PACKAGE
SEC1110/SEC1210
JTAG_CLK
SC_LED_ACT_N/JTAG_TDO
JTAG_TDI
RESET_N
13
14 SEC1110
15 (Top View QFN-16)
Thermal Slug
16 (must be connected to
VSS)
8
7
6
5
SC1_PRSNT_N/JTAG_TMS
SC1_VCC
SC1_RST_N
SC1_CLK
Indicates pins on the bottom of the device
2013 - 2016 Microchip Technology Inc.
DS00001561C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SEC1210.PDF ] | |
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