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PDF EM48BM0884VTA Data sheet ( Hoja de datos )
| Número de pieza | EM48BM0884VTA | |
| Descripción | 256Mb Synchronous DRAM | |
| Fabricantes | Eorex | |
| Logotipo |  |
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Revision History
Revision 0.1 (Aug. 2011)
- First release.
EM48BM0884VTA
Aug. 2011
1/20
www.eorex.com
1 page  
EM48BM0884VTA
Pin Description (Simplified)
Pin
38
19
37
23~26, 22, 29~36
20, 21
18
17
16
39
2, 5, 8, 11, 44,
47, 50, 53
1,14,27/
28,41,54
3, 9, 43, 49/
6, 12, 46, 52
4, 7, 10, 13, 15,
40, 42, 45, 48, 51
Name
CLK
/CS
CKE
A0~A12
BA0, BA1
/RAS
/CAS
/WE
DQM
DQ0~DQ7
VDD/VSS
VDDQ/VSSQ
NC
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A12) is determined by A0 to A12 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA9) is determined by A0 to A9 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
Aug. 2011
5/20
www.eorex.com
5 Page 
EM48BM0884VTA
Recommended Power On and Initialization
The following power on and initialization sequence guarantees the device is preconditioned to each users
specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on
voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. (CLK signal started at same
time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the
precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held
high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command
must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required, and these may be done before or after programming the Mode Register.
Aug. 2011
11/20
www.eorex.com
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