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PDF EM44CM1688LBA Data sheet ( Hoja de datos )
| Número de pieza | EM44CM1688LBA | |
| Descripción | 1Gb Double DATA RATE 2 SDRAM | |
| Fabricantes | Eorex | |
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eorex
EM44CM1688LBA
1Gb (8M×8Bank×16)
Double DATA RATE 2 SDRAM
Features
Description
• JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
• All inputs and outputs are compatible with
SSTL_18 interface.
• Fully differential clock inputs (CK,/CK) operation.
• 8 Banks
• Posted CAS
• Burst Length: 4 and 8.
• Programmable CAS Latency (CL): 3, 4 and 5.
• Programmable Additive Latency (AL):
0, 1, 2, 3 and 4.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL)
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available.
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination (ODT)
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Average Refresh Period 7.8us at lower than Tcase
85°C, 3.9us at 85°C < Tcase ≦ 95°C
• RoHS Compliance
• Partial Array Self-Refresh (PASR)
• High Temperature Self-Refresh rate enable
The EM44CM1688LBA is a high speed Double Date
Rate 2 (DDR2) Synchronous DRAM fabricated with
ultra high performance CMOS process containing
1,073,741,824 bits which organized as 8Mbits x 8
banks by 16 bits.
This synchronous device achieves high speed
double-data-rate transfer rates of up to 667
Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following
key DDR2 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) Off-Chip Driver (OCD) impedance adjustment
and On Die Termination (4) normal and weak
strength data output driver.
All of the control and address inputs are
synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
strobes (DQS and /DQS) in a source synchronous
fashion. The address bus is used to convey row,
column and bank address information in a /RAS and
/CAS multiplexing style.
The 1Gb DDR2 device operates with a single power
supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (13mmx9mm,
0.8mm x 0.8mm ball pitch).
Ordering Information
Part No
Organization
Max. Freq
EM44CM1688LBA-25F
64M X 16
tCK 5: DDR2-800Mhz 5-5-5
( Note )
Note : Speed ( tCK *) is in order of CL-tRCD-tRP
Package
TFBGA-84
Ball
Grade
Commercial
Pb
Free
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1 page  
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EM44CM1688LBA
B3,F3
G8,G2,H7,H3,H1,
H9,F1,F9,C8,
C2,D7,D3,D1,
D9,B1,B9
A1,E1,J9,M9,R1/
A3,E3,J3,N1,P9
A9,C1,C3,C7,C9,E
9,G1,G3,G7,G9/
A7,B2,B8,D2,D8,E
7,F2,F8,H2,H8
J1/J7
J2
A2,E2,L1,R3,R7,
R8
UDM,LDM
DQ0~15
VDD/VSS
VDDQ/VSSQ
VDDL/VSSDL
VREF
NC
to provide differential pair signaling to the system during both reads
and writes. An EMRS(1) control bit enables or disables all
complementary data strobe signals. In this data sheet, "differential
DQS signals" refers to A10 = 0 of EMRS(1) using LDQS/LDQS and
UDQS/UDQS. "single-ended DQS signals" refers to A10 = 1 of
EMRS(1) using LDQS and UDQS.
(Input Data Mask)
DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS. Although DM
pins are input only, the DM loading matches the DQ and DQS
loading.
(Data Input/Output)
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ and VSSQ are power supply for the output buffers.
(DLL Power Supply/DLL Ground)
VDDL and VSSDL are power supply for DLL circuits
(Reference Voltage)
SSTL_1.8 reference voltage
(No Connection)
No internal electrical connection is present.
Feb. 2009
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EM44CM1688LBA
AC Operating Test Characteristics (Continued)
(VDD=1.8V±0.1V, TA=0°C ~85°C)
Symbol
Parameter
tRPST
tRAS
tRC
tRFC
tRCD
tRP
tRRD
tCCD
tWR
tDAL
tXSRD
tXSNR
tXARD
tXARDS
tXP
tWTR
tRTP
tCKE
Read Postamble
Active to Precharge command period
Active to Active command period
Auto Refresh Row Cycle Time
Active to Read or Write delay
Precharge command period
Active bank A to B command period
Column address to column address
delay
Write recovery time
Auto Pre-charge write recovery +
pre-charge time
Exit self refresh to Read command
Exit self refresh to non-read command
Exit active power-down mode to Read
command (Fast exit)
Exit active power-down mode to Read
command (Slow exit)
Exit pre-charge power-down to any
non-read command
Internal Write to Read command delay
Internal Read to pre-charge delay
CKE minimum pulse width
tWPD Write to pre-charge delay(same bank)
tRPD Read to pre-charge delay(same bank)
tOIT OCD drive mode output delay
tREFI Average periodic refresh interval
-3
Min. Max.
0.4 0.6
45 70K
57.5
127.5
12.5
12.5
10
-
-
-
-
-
2-
15
tRP+
tWR
200
137.5
2
-
-
-
-
-
8-AL -
2
7.5
7.5
3
WL+
BL/2 +
tWR
AL+
BL/2+1
0
-
-
-
-
-
-
-
12
7.8
Unit
tCK
ns
ns
ns
ns
ns
ns
tCK
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
tCK
tCK
tCK
ns
us
Feb. 2009
11/29
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