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CD4099BMS Datasheet دیتاشیت PDF دانلود

دیتاشیت - Intersil Corporation - CMOS 8-Bit Addressable Latch

شماره قطعه CD4099BMS
شرح مفصل CMOS 8-Bit Addressable Latch
تولید کننده Intersil Corporation 
آرم Intersil Corporation 


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CD4099BMS شرح
CD4099BMS
December 1992
CMOS 8-Bit Addressable Latch
Features
Pinout
• High Voltage Type (20V Rating)
• Serial Data Input
CD4099BMS
TOP VIEW
• Active Parallel Output
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Q7 1
RESET 2
DATA 3
WRITE DISABLE 4
A0 5
A1 6
A2 7
VSS 8
16 VDD
15 Q6
14 Q5
13 Q4
12 Q3
11 Q2
10 Q1
9 Q0
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Multi-Line Decoders
• A/D Converters
Description
CD4099BMS 8-bit addressable latch is a serial input, parallel
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit
is addressed (by means of inputs A0, A1, A2) and when
WRITE DISABLE is at a low level. When WRITE DISABLE is
high, data entry is inhibited; however, all 8 outputs can be
continuously read independent of WRITE DISABLE and
address inputs.
Functional Diagram
WRITE DISABLE
DATA
4
3
A0 5
A1 6
A2 7
DECODER
8
RESET
2
VDD = 16
VSS = 8
8 LATCHES
9 Q0
10 Q1
11 Q2
12 Q3
13 Q4
14 Q5
15 Q6
1 Q7
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a
high level. When RESET is at a high level, and WRITE DIS-
ABLE is at a low level, the latch acts as a 1 of 8 demulti-
plexer; the bit that is addressed has an active output which
follows the data input, while all unaddressed bits are held to
a logic “0” level.
The CD4099BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-494
File Number 3333

قانون اساسیصفحه 10
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CD4099BMS CMOS 8-Bit Addressable Latch Intersil Corporation
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