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PDF VSC8164 Data sheet ( Hoja de datos )
| Número de pieza | VSC8164 | |
| Descripción | 2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux | |
| Fabricantes | Vitesse Semiconductor | |
| Logotipo |  |
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VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Features
• 2.488Gb/s 1:16 Demultiplexer
• Targeted for SONET OC-48 / SDH STM-16
Applications
• Supports FEC rates up to 2.7Gb/s
• Differential LVPECL Low Speed Interface
• Single +3.3V Supply
• 128 Pin 14x20mm PQFP Package
General Description
The VSC8164 is a 1:16 demultiplexer for use in SONET/SDH systems operating at a standard 2.488Gb/s
data rate or forward error correction (FEC) data rate up to 2.7Gb/s. The device operates using a single 3.3V
power supply, and is packaged in a thermally enhanced plastic package. The thermal performance of the
128PQFP allows the use of the VSC8164 without a heat sink under most thermal conditions.
VSC8164 Block DIagram
DI+
DI-
HSCLKI+
HSCLKI-
Divide by
16
Divide by
2
D0+
D0-
D15+
D15-
CLK16O+
CLK16O-
CLK32O+
CLK32O-
Functional Description
Low Speed Interface
The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D[15:0] with
accompanying differential LVPECL divide by 16 clock CLK16O± and divide by 32 clock CLK32O±. The low
speed LVPECL output drivers are designed to drive a 50Ω transmission line. The transmission line can be DC
terminated with a split end termination scheme (see Figure 1), or DC terminated by 50Ω to VCC-2V on each line
(see Figure 2). At any time, the equivalent split-end termination technique can be substituted for the traditional
50Ω to VCC-2V on each line. AC coupling can be achieved by a number of methods. Figure 3 illustrates an AC
coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the
downstream device were to have internal termination, the line to line 100Ω resistor may not be necessary. The
divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.
G52239-0, Rev. 3.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
1 page  
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b
= αSingle
Ended
a Swing
b
= αDifferential
Swing
a
* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing.
Differential swing is specified as equal in magnitude to single ended swing.
Table 1: AC Characteristics
Parameters
Description
Min Max Units
Conditions
tpdd
tpd32
Data valid from falling
edge of CLK16O+
CLK32O transition from
falling edge of CLK16O+
0 800 ps.
0 1.0 ns.
tDR, tDF
tCLKR, tCLKF
D[15:0]+/- rise and fall
times
CLK16O+/- rise and fall
times
CLK16OD CLK16O+/- duty cycle
distortion
DI+ setup time with respect
tdsu to falling edge of
HSCLKI+
tdh
DI+ hold time with respect
to falling edge of
HSCLKI+
HSCLKID HSCLKI+/- duty cycle
distortion
—
—
45
100
75
40
400
ps
20% to 80% into 50 Ohm load.
See Figure 7
250
ps
20% to 80% into 50 Ohm load.
See Figure 7
% of
55 clock High speed clock input at 2.488GHz
cycle
— ps
— ps
% of
60 clock
cycle
G52239-0, Rev. 3.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
5 Page 
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Pin Name I/O Level
Description
106
D1-
O
LVPECL
Low speed differential parallel data
107 VCC
- +3.3V typ Positive power supply pins
108
D0+
O
LVPECL
Low speed differential parallel data
109
D0-
O
LVPECL
Low speed differential parallel data
110 VEE
-
GND typ
Negative power supply pins
111
CLK16O-
O
LVPECL
Parallel clock output, complement
112
CLK16O+
O
LVPECL
Parallel clock output, true
113 VCC
- +3.3V typ Positive power supply pins
114
CLK32O-
O
LVPECL
Divided parallel clock output, complement
115
CLK32O+
O
LVPECL
Divided parallel clock output, true
116 NC - - No connect, leave unconnected
117 NC - - No connect, leave unconnected
118 NC - - No connect, leave unconnected
119 NC - - No connect, leave unconnected
120 NC - - No connect, leave unconnected
121 NC - - No connect, leave unconnected
122 NC - - No connect, leave unconnected
123 NC - - No connect, leave unconnected
124 NC - - No connect, leave unconnected
125 NC - - No connect, leave unconnected
126 NC - - No connect, leave unconnected
127 NC - - No connect, leave unconnected
128 NC - - No connect, leave unconnected
Note:
No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or nega-
tive power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent
damage to the device.
G52239-0, Rev. 3.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet VSC8164.PDF ] | |
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