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JCET - Dual Digital Transistors

Numéro de référence EMD2
Description Dual Digital Transistors
Fabricant JCET 
Logo JCET 





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EMD2 fiche technique
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
JC(T
Digital Transistors (Built-in Resistors)
EMD2 Dual Digital Transistors (NPN+NPN)
SOT-563
FEATURES
z Both the DTA124E chip and DTC124E chip in a package
z Mounting possible with SOT-563 automatic mounting machines
z Transistor elements are independent, eliminating interference
z Mounting cost and area be cut in half
Marking: D2
1
Absolute maximum ratings(Ta=25)
Parameter
Supply voltage
Input voltage
Output current
Power dissipation
Junction temperature
Storage temperature
Symbol
VCC
VIN
IO
IC(MAX)
Pd
Tj
Tstg
Limits
50
-10~40
30
100
150
150
-55~150
Unit
V
V
mA
mW
Electrical characteristics (Ta=25)
Parameter
Symbol Min. Typ Max. Unit
Conditions
Input voltage
VI(off)
VI(on)
0.5
V
3
VCC=5V, IO=100μA
VO=0.2V, IO=5mA
Output voltage
VO(on)
0.1 0.3 V
IO/II=10mA/0.5mA
Input current
II
0.36 mA
VI=5V
Output current
IO(off)
0.5 μA
VCC=50V, VI=0
DC current gain
GI 56
VO=5V, IO=5mA
Input resistance
R1 15.4 22 28.6 K
-
Resistance ratio
R2/R1
0.8
1
1.2
-
Transition frequency
fT
250 MHz VCE=10V, IE=5mA, f=100MHz
www.cj-elec.com
1
E,May,2015

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