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PDF CD4085BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4085BMS | |
| Descripción | CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4085BMS
December 1992
CMOS Dual 2 Wide 2 Input
AND-OR-INVERT Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium Speed Operation
- tPHL = 90ns
- tPLH = 125ns (Typ.) at 10V
• Individual Inhibit Controls
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4085BMS contains a pair of AND-OR-INVERT gates, each
consisting of two 2 input AND gates driving a 3 input NOR gate.
Individual inhibit controls are provided for both A-O-I gates..
The CD4085BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H5W
CD4085BMS
TOP VIEW
A1 1
B1 2
E1 = INHI + A1B1 + C1D1 3
E2 = INH2 + A2B2 + C2D2 4
A2 5
B2 6
VSS 7
Functional Diagram
10
INHIBIT 1
1
A1
2
B1
12
C1
13
D1
11
INHIBIT 2
5
A2
6
B2
8
C2
9
D2
14 VDD
13 D1
12 C1
11 INHIBIT 2
10 INHIBIT 1
9 D2
8 C2
3
E1
4
E2
E = INHIBIT + AB + CD
LOGIC 1 = HIGH
LOGIC 0 = LOW
VDD = 14
VSS = 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1046
File Number 3327
1 page  
Specifications CD4085BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Output Current (Source)
IOH5A
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
3, 4
GROUND
1, 2, 5-13
VDD
14
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
Note 1
3, 4
7 1, 2, 5, 6, 8-14
Dynamic Burn-
In Note 1
-
7
14
3, 4
1, 2, 5, 6, 8, 9,
10, 11
12, 13
Irradiation
Note 2
3, 4
7 1, 2, 5, 6, 8-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-1050
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4085BMS.PDF ] | |
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