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PDF UM6520A Data sheet ( Hoja de datos )
| Número de pieza | UM6520A | |
| Descripción | Peripheral Interface Adapter | |
| Fabricantes | UMC | |
| Logotipo |  |
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(l)UMC
UM6520 / UM6520A
Peripherald",',,""''"'"''''''''.''''' Interface Adapte,(PIA)
Features
• Direct replacement for Motorola MC6820
• Single +5V power supply
• Two 8-bit bi-directional I/O ports with individual data
direction control
• CMOS-compatible peripheral port A lines
• Automatic "handshake.' control of data transfers
• Programmable interrupt capability
• Automatic initialization on power up
• 1 and 2 MHz versions
General Description
The UM6520/A peripheral Interface Adapter (PIA) is
designed to provide a broad range of peripheral control to
microcomputer systems. Control of peripheral devices is
accomplished through two 8-bit bi-directional I/O ports.
Each I/O line may be programmed to be either an input
or an output. In addition, four peripheral control lines
are provided to perform "handshaking" during data
transfers.
Pin Configuration
Block Diagram
VSS
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CB1
CB2
VCC
CA1
CA2
IROA
IROB
RSO
RS1
RES
DO
01
02
03
04
05
06
07
r/J2
CS1
CS2
CSO
RlW
MICRO-
PROCESSORS
UM650X
1881T
DATA BUS
CONTROL
UM6520!
6520A
CONTROL
8-BIT
DATA PORT
8-BIT
DATA PORT
PERIPHERAL
DEVICES-
PRINTERS,
DISPLAYS, ETC.
CONTROL
7-41
1 page  
Interface Signal Description
FfES(Resed
This signal is used to initialize the PIA. A low signal on
the RES input causes all internal registers to be cleared.
ifh (Input Clock)
This input is the system <1>2 clock and is used to trigger
all data transfers between the microprocessor and the
PIA.
R/W (ReadlWrite)
This signal is generated by the microprocessor and is used
to control the direction of data transfers. A high on the
R/IN signal permits the processor to read data supplied by
the PIA; a low on the R/W signal permits the processor to
Write into the PIA.
IROA, IAOB (Interrupt Requests)
I ROA and I ROB are interrupt lines generated by the PIA
for ports A and B respectively.· These signals are active
low signals and have open-drain outputs, thus allowing
multiple I RO signals from multiple PIA's to be wire-ORed
together before connecting to the processor I RQ signal
input.
.
UM6520 / UM6520A
0 0 -07 (Data Bus)
These eight data bus lines are used to transfer data informa-
tion between the processor and the PIA. These signals
are bi-directional and are normally highimpedance except
when selected for a read operation.
CSO, CS1, CS2 (Chip Selects)
The PIA is selected when CSO and CS1 are high and CS2
is low. These three chip select lines are normally connected
to the processor address lines either directly or through
external decoder circuits.
RSO, RS1 (Register Selects)
These two signals are used to select the various registers
inside the PIA.
Internal Architecture
The UM6520/A is organized into two independent sections
referred to as the "A Side" and the "B Side." Each section
consists of a Control Register.(CRA, CRB), Data Direction
Register (DORA, DDRB), Output Register (ORA, ORB),
Interrupt Status Control and the buffers necessary to drive
the Peripheral Interface buses. Figure 3 is a block diagram
of the UM6520/A.
IROA-------------------------------------------------j INTERRUPTSTATUS
CONTROL A
CAl
CA2
OO _ _--~~-------,
01 __- - - - - .
02-------.1
03 _-----.I
04_------.
05_
OATA BUS
BUFFERS
(OBB)
06-------1
07 _ _- -_ _~_ _~--~
PERIPHERAL
OUTPUT
REGISTER A
(ORA)
r-----~------~---PAO
_PAl
PA2
PA3
PA4
PA5
PA6
PA7
OATAINPUT
REGISTER
(OIR)
PERIPHERAL
OUTPUT
REGISTER B
(ORB)
CSO
CSl
CS2
RSO
- - -..RSl
RiW
ENABLE - - - - -
RESET
CHIP
SELECT
ANO
R!W
CONTROL
INPUT BUS
L -_ _ _ _ _ _--. INTERRUPT STATUS
.....------------..IROB4-----------------------------------------------~
CONTROL B,
PB2
PB3
PB4
PB5
PB6
PB7
CBl
CB2
Figure 3. UM6520/UM6520A Block Diagram
7-45
5 Page 
UM6520/ UM6520A
CA2/CB2 INPUT MODES
CRA (CRB)
BitS Bit 4 Bit 3
000
00 1
Active Transition
of Input Signal*
Negative
Negative
0 10
0 11
Positive
Positive
·IRQA (lRQB) Interrupt Outputs
Disable - remains high
Enable - goes low when bit 6 in CRA (CRB) is set by active
transition of signal on CA2 (CB2)
Disable - remains high
Enable - as explained above
*Note: Bit 6 of CRA (CRB) will be set to a logic 1 by an active transition of the CA2 (CB2) signal. This is independent of
the state of Bit 3 in CRA (CRB).
CA2 OUTPUT MODES
BitS
1
CRA
Bit4
0
Bit 3
0
Mode
"Handshake"
on Read
1 0 1 Pulse Output
1 1 0 Manual Output
1 1 1 Manual Output
Descriptions
CA2 is set high on an active transition of the CA 1 interrupt
input signal and set low by a microprbce~sor "Read A Data"
operation. This allows positive control of data transfers from
the peripheral device to the microprocessor.
CA2 goes low for one cycle after a "Read A Data" operation.
Th is pulse can be used to signal the peripheral device that data
was taken.
CA2 set low
CA2 set high
CB2 OUTPUT MODES
Bit 5
1
CRB
Bit4
a
Bit 3
0
10
1
110
111
Mode
Descriptions
"Handshake"
on Write
Pulse Output
Manual Output
Manual Output
CB2 is set low on microprocessor "Write B Data" operation
and is set high by an active transition of the CB1 interrupt
input signal. This allows positive control of data transfers
from the microprocessor to the peripheral device.
CB2 goes low for one cycle after a microprocessor "Write B
Data" operation. This can be used to signal the peripheral
device that data is available.
CB2 set low
CB2 set high
Figure 8. Summary of Operation of Control Lines
7-51
11 Page | ||
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| PDF Descargar | [ Datasheet UM6520A.PDF ] | |
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