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PDF LAN83C185 Data sheet ( Hoja de datos )
| Número de pieza | LAN83C185 | |
| Descripción | High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver | |
| Fabricantes | SMSC Corporation | |
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LAN83C185
High Performance Single
Chip Low Power 10/100
Ethernet Physical Layer
Transceiver (PHY)
PRODUCT FEATURES
Single Chip Ethernet Phy
Fully compliant with IEEE 802.3/802.3u standards
10BASE-T and 100BASE-TX support
Supports Auto-negotiation and Parallel Detection
Automatic Polarity Correction
Integrated DSP with Adaptive Equalizer
Baseline Wander (BLW) Correction
Media Independent Interface (MII)
802.3u compliant register functions
Vendor Specific register functions
Datasheet
Comprehensive power management features
General power-down mode
Energy Detect power-down mode
Low profile 64-pin TQFP package; lead-free RoHS
compliant package also available
Single +3.3V supply with 5V tolerant I/O
0.18 micron technology
Low power consumption
Operating Temperature 0° C to 70° C
Internal +1.8V Regulator
Applications
LAN on Motherboard
10/100 PCMCIA/CardBus Applications
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems And Set-Top Boxes
Digital Televisions
Wireless Access Points
ORDER NUMBERS:
LAN83C185-JD FOR 64-PIN TQFP PACKAGE
LAN83C185-JT FOR 64-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGE
SMSC LAN83C185
DATASHEET
Revision 0.8 (06-12-08)
1 page  
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
List of Figures
Figure 1.1
Figure 2.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 5.1
Figure 7.1
LAN83C185 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Relationship Between Received Data and Some MII Signals . . . . . . . . . . . . . . . . . . . . . . . . 20
MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MDIO Timing and Frame Structure - WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PHY Address Strapping on LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
64 Pin TQFP Package Outline, 10X10X1.4 Body, 2 MM Footprint . . . . . . . . . . . . . . . . . . . . 60
SMSC LAN83C185
5
DATASHEET
Revision 0.8 (06-12-08)
5 Page 
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 3 Pin Description
This chapter describes in detail the functionality of each of the five main architectural blocks.
The term “block” defines a stand-alone entity on the floor plan of the chip.
3.1 I/O Signals
I – Input. Digital TTL levels.
O – Output. Digital TTL levels.
AI – Input. Analog levels.
AO – Output. Analog levels.
AI/O – Input or Output. Analog levels.
Note: Reset as used in the signal descriptions is defined as nRST being active low.
Configuration inputs are listed in parenthesis.
PIN NO.
SIGNAL NAME
41 TXD0
42 TXD1
39 TX_EN
35 RX_ER
(RXD4)
47 COL
32 RXD0
31 RXD1
44 TXD2
45 TXD3
Table 3.1 MII Signals
TYPE
DESCRIPTION
I Transmit Data 0: Bit 0 of the 4 data bits that are accepted
by the PHY for transmission.
I Transmit Data 1: Bit 1 of the 4 data bits that are accepted
by the PHY for transmission.
I Transmit Enable: Indicates that valid data is presented
on the TXD[3:0] signals, for transmission.
O Receive Error: Asserted to indicate that an error was
O detected somewhere in the frame presently being
transferred from the PHY.
In Symbol Interface (5B Decoding) mode, this signal is the
MII Receive Data 4: the MSB of the received 5-bit symbol
code-group.
O MII Collision Detect: Asserted to indicate detection of
collision condition.
O Receive Data 0: Bit 0 of the 4 data bits that are sent by
the PHY in the receive path.
O Receive Data 1: Bit 1 of the 4 data bits that are sent by
the PHY in the receive path.
I Transmit Data 2: Bit 2 of the 4 data bits that are accepted
by the PHY for transmission.
I Transmit Data 3: Bit 3 of the 4 data bits that are accepted
by the PHY for transmission.
SMSC LAN83C185
11
DATASHEET
Revision 0.8 (06-12-08)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN83C185.PDF ] | |
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