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PDF LAN88730 Data sheet ( Hoja de datos )
| Número de pieza | LAN88730 | |
| Descripción | Small Footprint MII/RMII 10/100 Ethernet Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN88730 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN88730
Small Footprint MII/RMII 10/100 Ethernet Transceiver for
Automotive Applications
Highlights
• Designed and tested for automotive applications
• Single-Chip Ethernet Physical Layer Transceiver
(PHY)
• Comprehensive flexPWR® technology
- Flexible power management architecture
- LVCMOS Variable I/O voltage range: +1.8 V to
+3.3 V
- Integrated 1.2 V regulator
• HP Auto-MDIX support
• Small footprint 32-pin VQFN, RoHS-compliant
package (5 x 5 x 0.9 mm height)
• Deterministic 100 Mb internal loopback latency
(MII Mode)
Target Applications
• Diagnostic interface
(for dealership service bay)
• Fast software download
(e.g., OBD connector)
• Gateway service interface
(dealership, aftermarket repair shop)
• In-Vehicle engineering development interface
• Vehicle manufacturing test interface
(production plant assembly line)
• Legislated inspections
(emissions check, safety inspections)
Key Benefits
• High-performance 10/100 Ethernet transceiver
- Compliant with IEEE802.3/802.3u (Fast Ethernet)
- Compliant with ISO 802-3/IEEE 802.3
(10BASE-T)
- Loop-back modes
- Auto-negotiation
- Automatic polarity detection and correction
- Link status change wake-up detection
- Vendor specific register functions
- Supports both MII and the reduced pin count RMII
interfaces
• Power and I/Os
- Various low power modes
- Integrated power-on reset circuit
- Two status LED outputs
- May be used with a single 3.3 V supply
• Additional Features
- Ability to use a low cost 25 MHz crystal for
reduced BOM
• Packaging
- 32-pin VQFN (5 x 5 mm), RoHS-compliant
package with MII and RMII
• Environmental
- Automotive grade A temp. support
(-40°C to +85°C)
- Automotive grade B temp. support
(-40°C to +105°C)
2012-2015 Microchip Technology Inc.
DS60001256B-page 1
1 page  
FIGURE 1-2:
ARCHITECTURAL OVERVIEW
MODE[0:2]
nRST
RMIISEL
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Mode Control
Reset Control
Auto-
Negotiation
SMI Management
Control
100M RX
Logic
10M RX
Logic
100M TX
Logic
100M
Transmitter
Transmitter
10M TX
Logic
10M
Transmitter
DSP System:
Clock
Data Recovery
Equalizer
Receiver
10M PLL
Analog-to-
Digital
100M PLL
Squeltch
& Filters
LAN88730
LAN88730
HP Auto-MDIX
TXP/TXN
RXP/RXN
MDIX
Control
PLL
Interrupt
Generator
LEDs
XTAL1/CLKIN
XTAL2
nINT
LED1
LED2
Central Bias
RBIAS
PHY Address
Latches
PHYAD[0:2]
2012-2015 Microchip Technology Inc.
DS60001256B-page 5
5 Page 
LAN88730
TABLE 2-4: ETHERNET PINS (CONTINUED)
Num Pins
1
1
1
Name
Ethernet
TX/RX Nega-
tive Channel
1
Ethernet
TX/RX Posi-
tive Channel
2
Ethernet
TX/RX Nega-
tive Channel
2
Symbol
TXN
RXP
RXN
Buffer Type
Description
AIO Transmit/Receive Negative Channel 1
AIO Transmit/Receive Positive Channel 2
AIO Transmit/Receive Negative Channel 2
TABLE 2-5: MISCELLANEOUS PINS
Num Pins
1
Name
External
Crystal
Input
External
Clock Input
1 External
Crystal Out-
put
1 External
Reset
Symbol
XTAL1
Buffer Type
Description
ICLK
External crystal input
CLKIN
XTAL2
ICLK
OCLK
Single-ended clock oscillator input.
Note:
When using a single ended clock
oscillator, XTAL2 should be left uncon-
nected.
External crystal output
nRST
VIS
(PU)
System reset. This signal is active low.
TABLE 2-6: ANALOG REFERENCE PINS
Num Pins
1
Name
External 1%
Bias Resistor
Input
Symbol
RBIAS
Buffer Type
Description
AI This pin requires connection of a 12.1 kΩ (1%)
resistor to ground.
Refer to the LAN88730 reference schematic for
connection information.
Note:
The nominal voltage is 1.2 V and the
resistor will dissipate approximately
1 mW of power.
2012-2015 Microchip Technology Inc.
DS60001256B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN88730.PDF ] | |
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