UM8312 Datasheet PDF - UMC
| Part Number | UM8312 | |
| Description | Double Row Buffer | |
| Manufacturers | UMC | |
| Logo |  |
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SUMO
UM8312
Double Row Buffer(DRB)
Features
• Low cost solution to CRT memory contention problem
• Provides enhanced processor throughput for CRT
display systems
• Replaces shift registers or several RAM and counter
IC's in CRT display system
• Permits display of one data row while next data row is
being loaded
• Data may be written into buffer at less than the video
painting rate
• Double data row buffer permits second data row to
be loaded anytime during the display of the preceding
data row
• Permits active video 'on all scan lines of data row
• Dynamically variable numbe~ of characters per data
Row-... 64, 80, 132, .... up to a maximum of 135
• Cascadab Ie for data rows greater than 135 characters
• Stackable for "I nvisible Attributes" or character widths
of greater than 8 Bits
• Three-state outputs
• Up to 4 MHz read/write data rate
• Compatible with UM9007 and other CRT controllers
• 28 pin dual-in-line package
• +5 volt only power supply
• TT L compatible
General Description
The UM8312 Double Row Buffer (ROB) provides a low
cost solution to memory contention between the system
processor and the CRT controller in video display systems.
The UM8312 ORB is a RAM-based buffer which provides
two rows of buffering. It appears to the system as two
octal shift registers of dynamically variable length (2-135
bytes) plus steering logic.
The UM8312 permits the loading of one data row while
the previous data row is being displayed. The loading of
data may take place during any of the scan line times of
the data row. This relaxed time-constraint allows the
processor to perform additional processing on the data or
service other high priority interrupt conditions (such as a
Floopy Disk DMA request) which may occur during a single
video scan line. The result is enhanced processor throughput
and flicker-free display of data.
Pin Configuration
Block Diagram
DIN2
DIN1
DINO
DOUT7
DOUT6
DOUT5
DOUT4
Vcc
DOUT3
DOUT2
DOUT1
DOUTO
DIN7
DIN6
DIN3
WCLK
OE
WEN2
WEN1
GND
ROF
WOF
REN
CLRCNT
TOG
RCLK
DIN4
DIN5
READ/WRITE
CONTROL
TOG
CLRCNT
OE
_RCLK
REN
WCLK
WENl
WEN2
ROF
WOF
5-71
|
| |
 
(DUMC
+5V
DATA BUS
• WENl
WEN2
RCLK
WCLK
REN UM8312 "A"
~
) DIN7-0
v
CLRCNT
TOG
DOUT7-0
ROF t - - -
WOF~
UM8312
DATA BUS
~ WENl
WEN2
RCLK
twcLK
REN UM8312 "B"
)" DIN7-0
v
-~ CLRCNT
TOG
DOUT7-0
Figure 3. UM8312 Cascaded Configuration For Data Row Lengths Up To 270 Characters
INTR k - - - - - - - - - ,
PROCESSOR ACK / - - - - - - - - ,
OMARQ .....- - - - ,
ADDR DATA
DMAR ACK
MEMORY l,r_ _ _ _ _-.-.-_-,/l vAll -<I>
INT
ROM
ADDRESS BUS
UM9007 CRTC
=VHSS I-_ _ _---;~} ~~N ITOR
RAM
~LV_D_7~-O~ ~SL~G ~S~LD CC~L~K ~VIDEO RAM 1'..-----,/1
1.-_ _...... "
________ __
________________ ________
BUFFER
CONTROLS
Lr +SHIFT
REGISTER
DATA
BUS
.-----~ I~_ _ _ _ _~--------,
.----~ I~_____- - - - - - - - .
I SCAN LINE DATA
WCLK RCLK
,J ~ rr-:A~3~_A:;::O--~C~H~A:!:R~A~CT!!E~RlJW~IQD!!TH~
1--------",/11
CLOCK
GENER-
r - v~ DIN7_0UM831~OUT7_0 f------'\ CH~~CTER
r----v'
I"11-A4
f-----
Iv ATOR
DOUBLE ROW BUFFER
1.-_ _......-
=
+ ++
CHAR
~ DIN7-0 UM8312
CODE
CHARACTER ATTRIBUTS
A7-0
UM8321
VDCf4:--
SHLD .....- - - - '
v'
DOUT7-0 t - - - - - - - - - - - - ' \ . I A T T R I B U T E S VIDE0I--_ _ _ _ _ TO MONITOR
t-----------,/IVIDEO ATTRIBUTES
DOUBLE ROW BUFFER
CONTROLLER
Figure 4. UM8312 Configured With The UM9007 CRTC And The UM8321 CRT VAC
5-75
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| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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