|
|
PDF UM6845E Data sheet ( Hoja de datos )
| Número de pieza | UM6845E | |
| Descripción | CRT Controller | |
| Fabricantes | UMC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UM6845E (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
(l)UMC
UM6845£/UM6845£A/UM6845£B
CRT Controller
Features
• Single + 5 volt (± 5%) power supply
• Alphanumeric and limited graphics capabilities
• Fully programmable display (rows, columns, blanking,
etc.).
• Interlaced or non-interlaced scan
• 50/60 Hz operation
• Fully programmable cursor
• External light pen capability
• Capable of addressing up to 16K character Video
Display RAM
• No DMA required
• Pin-compatible with MC6845R
• Row/Column or straight-binary' addressing for Video
Display RAM
• Video Display RAM may be configured as part of
microprocessor memory field or independently slaved
to 6845
• Internal status register
3.7 MHz character clock
• Transparent address mode
General Description
The UM6845E is a CRT Controller intended to provide
capability for interfacing and 8 or 16 bit microprocessor
family to CRT or TV-type raster scan displays. A unique
feature is the inclusion of several modes of operation,
so that the system designer can configure the system
with a wide assortment of techniques.
Pin Configuration
GND
RES
lPEN
CCO/MAO
CC1/MAl
CC2/MA2
CC3/MA3
CC4/MA4
CC5/MA5
CC6/MA6
CC7/MA7
CRO/MA8
CR1/MA9
CR2/MA10
CR3/MAll
CR4/MA12
CR5/MA13
DISPLAY ENABLE
CURSOR
VCC
Block Diagram
VSYNC
HSYNC
RAO
RAl
RA2
RA3
RA4
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
CS
RS
E
R/W
CClK
VCC GND
DBO-DB7
E
R/W
CS
RS - - _ _ .
HSYNC
VSYNC
DISPLAY ENABLE
CURSOR
LPEN
CClK
RES
\MAO-MA13 RAO-RA4/
VIDEO DISPLAY RAM AND CHARACTER ROM
5-39
1 page  
eUMC
UM6845£ / UM6845£A / UM6845£B
MPU Interface Signal Description
E (Enable)
The enable signal is the system input and is used to trigger
all data transfers between the system microprocessor and
the UM6845E. Since there is no maximum limit to the
allowable E cycle time, it is not necessary for it to be a
continuous clock. This capability permits the UM6845E
to be easi Iy interfaced to non-6500-compatible micro-
processors.
R/W (Read/Write)
The R/Wsignal is generated by the microporocessor and is
used to control the direction of data transfers. A high on
the R/W pin allows the processor to read the data supplied
by the UM6845E, a low on the R/W pin allows a write to
the UM6845E.
CS (Chip Select)
The Chip Select input is normally connected to the pro-
cessor address bus either directly or through a decoder.
The UM6845E is selected when CS is low.
RS (Register Select)
The Register Select input is used to access internal registers.
A low on this pin permits write into the Address Register
and reads from the Status Register. The contents of the
Address Register is the identity of the register accessed
when RS is high.
DB9-DB7 (Data Bus)
The DBo-DB7 pins are the eight data lines used for transfer
of data between the processor and the UM6845E. These
lines are bi-directional and are normally high-impedance
except during read/write cycles when the chip is selected.
ENABLE may be delayed by one character time by setting
bit 4 of R8 to a "1 "
CURSOR
The CU RSOR signal is an active-high output and is used
to indicate when the scan coincides with the programmed
cursor position. The cursor position may be programmed
to be any character in the address field. Furtherillore,
with in the character, the cursor may be programmed to
be any block of scan lines, since the start scan line and the
end scan line are both programmable. The CURSOR
position may be delayed by one character time by setting
bit 5 of R8 to a "1"
LPEN
The LPEN signal is an edge-sensitive Input and is used to load
the internal Light Pen Register with the contents of the
Refresh Scan Counter at the time the active edge occurs.
The active edge of LPEN is the low-to-high transition.
CCLK
The CCLK signal is the character timing clock input and is
used as the time base for all internal count/control func-
tions.
RES
The RES signal is an active-low input used to initialize all
internal scan counter circuits. When RES is low, all internal
counters are stopped and cleared, all scan and video outputs
are low, and control registers are unaffected. RES must
stay low for at least one CCLK period. All scan timing
is initiated when RES goes high. In this way, RES can
be used to synchronize display frame timing with line
frequency.
Video I nterface Signal Description
HSYNC (Horizontal Sync)
The HSYNC signal is an active-high output used to deter-
mine the horizontal position of displayed text. It may
drive a CRT monitor directly or may be used for composite
video generation. HSYNC time position and width are
fully programmable.
VSYNC (Vertical Sync)
The VSYNC signal is an active-high output used to deter-
mine the vertical position of displayed text. Like HSYNC,
VSYNC may be used to drive a CRT monitor or composite
video generation circuits. VSYNC position and width are
both fully programmable.
DISPLAY ENABLE
The DISPLAY ENABLE signal is an active-high output
and is used to indicate when the UM6845E is generating
active display information. The nu mber of horizontal
displayed characters and the number of vertical displayed
characters are both fully programmable and together are
used to generate the DISPLAY ENABLE signal. DISPLAY
Memory Address Signal Description
MAO-MA13 (Video Display RAM Address Lines)
These signals are active-high outputs and are used to address
the Video Display RAM for character storage and display
operations. The starting scan address is fully programmable
and the ending scan address is determined by the total
number of characters displayed, .which is also program-
mable, In terms of characters/line and lines/frame.
There are two selectable address modes for MAO-MA 13:
• Binary
Characters are stored in successive memory locations.
Thus, the software must be developed so ·that row and
column co-ordinates are translated to sequentially
numbered addresses for video display memory opera-
tions.
• Row/Column
In this mode, MAO-MA7 function as column addresses
CCO-CC7, and MA8-MA13, as row addresses CRO-CR5.
In this case, the software may handle addresses in terms
of row and column locations, but additional address
compression circuits are needed to convert CCO-CC7
and CRO-CR5 into a memory-efficient binary scheme.
5-43
5 Page 
(l)UMC
UM6845£ / UM6845£A / UM6845£8
2. Transparent Memory Addreessing.
For this mode, the display RAM is not directly acces·
sible by the MPU, but is controlled entirely by the
UM6845E. All MPU accesses are made via the UM6845E
and a small amount ·of external circuits. Figure 6
shows the system configuration for this approach.
MPU
SYSTEM
BUS
UM6845E
CRT CONTROLLER
RA4
MAO-MA13
RAO-RA3
UPDATE
STROBE
DISPLAY/UPDATE SCAN LINE
ADDRESS
COUNT
MPU
DATA
BUS
DATA
HOLD
LATCH
CHARACTER
DATA
CHARACTER
GENERATOR
ROM
CHARACTER
DATA
Figure 6. Transparent Memory Addressing System Configuration (Data Hold Latch
needed for HorizontalNertical Blanking updates, only).
Memory Contention Schemes for Shared Memory
Addressing
From the diagram of Figure 4, it is clear that both the
UM6845E and the system MPU must be capable of
addressing the video display memory. The UM6845E
repetitively fetches character information to generate
the video signals in order to keep the screen display active.
The MPU occasionally accesses the memory to change
the displayed information or to read out current data
characters. Three ways of resolving this dualcontention
requirement are apparent:
• MPU Priority
In this technique, the address lir")es to the video display
memory are normally driven by the UM6845E unless
the MPU needs access, in which case the MPU addresses
immediately overried those from the UM6845E and
the MPU has immediate access.
• </> 11 </>2 Memory Interleaving
This method permits both the UM6845E and the MPU
access to the video display memory by timesharing
via the system </> 1 and </> 2 clocks. During the </> 1
portion of each cycle (the time when E is low), the
UM6845E address outputs are gated to the video display
memory. In the </>2 time, the MPU address lines are
switched in. In this way, both the UM6845E and the
MPU have unimpeded access to the memory. Figure 7
illustrates the timings.
• Vertical Blanking
With this approach, the address circuitry is identical
to the case for MPU Priority updates. The only dif-
ference is that the Vertical Retrace status bit (bit 5
of the Status Register) is used by the MPU so that access
to the video display memory is only made during vertical
blanking time (when bit 5 is a "1"). In this way, no
visible screen perturbations result.
5-49
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet UM6845E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UM6845 | CRT Controller | UMC |
| UM6845A | CRT Controller | UMC |
| UM6845B | CRT Controller | UMC |
| UM6845E | CRT Controller | UMC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |