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PDF IDT82V2051E Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2051E | |
| Descripción | SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
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SINGLE CHANNEL E1 SHORT
HAUL LINE INTERFACE UNIT
IDT82V2051E
FEATURES
• Single channel E1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
• Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS error
counter
- Analog loopback, Digital loopback, Remote loopback
• Short circuit protection and internal protection diode for line
drivers
• AIS (Alarm Indication Signal) detection
• Supports serial control interface, Motorola and Intel Multiplexed
interfaces and hardware control mode
• Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2041E T1/E1/J1 Short Haul LIU
• Package:
Available in 44-pin TQFP packages
Green package options available
DESCRIPTION
The IDT82V2051E is a single channel E1 Line Interface Unit. The
IDT82V2051E performs clock/data recovery, AMI/HDB3 line decoding and
detects and reports the LOS conditions. An integrated Adaptive Equalizer
is available to increase the receive sensitivity and enable programming of
LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform
Shaper. There is one Jitter Attenuator, which can be placed in either the
receive path or the transmit path. The Jitter Attenuator can also be disabled.
The IDT82V2051E supports both Single Rail and Dual Rail system inter-
faces. To facilitate the network maintenance, a PRBS generation/detection
circuit is integrated in the chip, and different types of loopbacks can be set
according to the applications. Two different kinds of line terminating imped-
ance, 75 Ω and 120 Ω are selectable. The chip also provides driver short-
circuit protection and internal protection diode. The chip can be controlled
by either software or hardware.
The IDT82V2051E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
December 9, 2005
DSC-6528/2
1 page  
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 ohm.................................................................... 16
Transmit Waveform Value For E1 120 ohm.................................................................. 16
Impedance Matching for Transmitter ............................................................................ 17
Impedance Matching for Receiver ................................................................................ 18
Criteria of Starting Speed Adjustment........................................................................... 22
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 22
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 23
AIS Condition ................................................................................................................ 23
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 24
EXZ Definition ............................................................................................................... 27
Interrupt Event............................................................................................................... 31
Register List and Map ................................................................................................... 32
ID: Device Revision Register ........................................................................................ 33
RST: Reset Register ..................................................................................................... 33
GCF: Global Configuration Register ............................................................................. 33
TERM: Transmit and Receive Termination Configuration Register .............................. 33
JACF: Jitter Attenuation Configuration Register ........................................................... 34
TCF0: Transmitter Configuration Register 0 ................................................................. 35
TCF1: Transmitter Configuration Register 1 ................................................................. 35
TCF2: Transmitter Configuration Register 2 ................................................................. 35
TCF3: Transmitter Configuration Register 3 ................................................................. 36
TCF4: Transmitter Configuration Register 4 ................................................................. 36
RCF0: Receiver Configuration Register 0..................................................................... 37
RCF1: Receiver Configuration Register 1..................................................................... 37
RCF2: Receiver Configuration Register 2..................................................................... 38
MAINT0: Maintenance Function Control Register 0...................................................... 39
MAINT1: Maintenance Function Control Register 1...................................................... 39
MAINT6: Maintenance Function Control Register 6...................................................... 39
INTM0: Interrupt Mask Register 0 ................................................................................. 41
INTM1: Interrupt Masked Register 1 ............................................................................. 41
INTES: Interrupt Trigger Edge Select Register ............................................................. 42
STAT0: Line Status Register 0 (real time status monitor)............................................. 43
STAT1: Line Status Register 1 (real time status monitor)............................................. 44
INTS0: Interrupt Status Register 0 ................................................................................ 45
INTS1: Interrupt Status Register 1 ................................................................................ 45
CNT0: Error Counter L-byte Register 0......................................................................... 46
CNT1: Error Counter H-byte Register 1 ........................................................................ 46
Hardware Control Pin Summary ................................................................................... 47
Absolute Maximum Rating ............................................................................................ 49
Recommended Operation Conditions ........................................................................... 49
List of Tables
5 December 9, 2005
5 Page 
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name Type Pin No.
Description
INT O
20 INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. These interrupt sources can be
masked individually via registers (INTM0, 14H) and (INTM1, 15H). The interrupt status is reported via the registers (INTS0,
19H) and (INTS1, 1AH).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
INT_PIN[1:0] (GCF, 02H).
RXTXM0
SCLK
I
I
RXTXM0
See RXTXM1 above.
25 SCLK: Shift Clock
In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sam-
pled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the falling edge of
SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin is low.
ALE ALE: Address Latch Enable
In parallel microcontroller interface mode with multiplexed Intel interface, the address on AD[7:0] is sampled into the device on
the falling edge of ALE.
AS AS: Address Strobe
In parallel microcontroller interface mode with multiplexed Motorola interface, the address on AD[7:0] is latched into the device
on the falling edge of AS.
LP1
SDI I
LP[1:0]: Loopback mode select
When the chip is configured by hardware, this pin is used to select loopback operation modes:
• 00= no loopback
• 01= analog loopback
• 10= digital loopback
• 11= remote loopback
24 SDI: Serial Data Input
In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sam-
pled by the device on the rising edge of SCLK.
WR WR: Write Strobe
In Intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data on
AD[7:0] is sampled into the device in a write operation.
R/W R/W: Read/Write Select
In Motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation.
LP0 LP0
See LP1 above.
Pin Description
11 December 9, 2005
11 Page | ||
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