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PDF IDT82V2048S Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2048S | |
| Descripción | OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
| Logotipo |  |
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OCTAL T1/E1 SHORT HAUL LINE
INTERFACE UNIT WITH SINGLE
ENDED OPTION
IDT82V2048S
FEATURES
! Fully integrated octal T1/E1 short haul line interface which
supports 100 Ω T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω
E1 coaxial applications
! Optional Single Ended receive termination LIU on RTIPn/
RRINGn for 75 Ω E1 coaxial applications
! Selectable Single Rail mode or Dual Rail mode and AMI or
B8ZS/HDB3 encoder/decoder
! Built-in transmit pre-equalization meets G.703 & T1.102
! Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications
! SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
! Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
! ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
! Low impedance transmit drivers with high-Z
! Selectable hardware and parallel/serial host interface
! Local, Remote and Inband Loopback test functions
! Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
! JTAG boundary scan for board test
! 3.3 V supply with 5 V tolerant I/O
! Low power consumption
! Operating temperature range: -40°C to +85°C
! Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
RTIPn
RRINGn
TTIPn
TRINGn
G.772
Monitor
Analog
Peak
Loopback Detector
Line
Driver
Clock
Generator
Slicer
LOS
Detector
CLK&Data
Recovery
(DPLL)
Digital
Loopback
Waveform
Shaper
Transmit
All Ones
Control Interface
One of Eight Identical Channels
Jitter
Attenuator
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Remote
Loopback
IBLC
Detector
AIS
Detector
B8ZS/
HDB3/AMI
Encoder
IBLC
Generator
Register
File
JTAG TAP
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
TCLKn
TDn/TDPn
BPVIn/TDNn
VDDIO
VDDT
VDDD
VDDA
Figure-1 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
September 2005
DSC-6969/-
1 page  
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
Pin No.
Type
TQFP144 PBGA160
Description
Transmit and Receive Digital Data Interface
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is
37
30
N2
L2
sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code
rules before being transmitted to the line.
80
73
108
101
8
L13
N13
B13
D13
D2
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Single Rail mode 2 (see Table-2 on page 14 and Table-3 on page
14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on
TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.
I
1 B2 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
38
31
79
N3
L3
L12
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail
mode is as the follow:
72 N12
TDPn
TDNn
Output Pulse
109 B12 0 0 Space
102 D12 0 1 Negative Pulse
7 D3
1 0 Positive Pulse
144 B3
1 1 Space
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into Single Rail mode 1 (see Table-2 on page 14 and Table-3 on page 14).
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
36 N1 lows:
29
L1 MCLK
TCLKn
Transmit Mode
81
L14 Clocked
Clocked
Normal operation
I
74
107
N14
B14
Clocked
High (≥ 16 MCLK)
Transmit All Ones (TAOS) signals to the line side in the corresponding
transmit channel.
100 D14 Clocked Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.
9 D1
TCLKn is clocked Normal operation
2 B1
TCLKn is high Transmit All Ones (TAOS) signals to the line side
(≥ 16 TCLK1) in the corresponding transmit channel.
High/Low
TCLK1 is clocked
TCLKn is low
(≥ 64 TCLK1)
Corresponding transmit channel is set into power
down state.
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
High/Low
TCLK1 is unavail-
able.
All eight transmitters (TTIPn & TRINGn) will be in high-Z.
5
5 Page 
IDT82V2048S OCTAL T1/E1 SHORT HAUL LIU WITH SINGLE ENDED
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
TDO
TDI
VDDIO
GNDIO
VDDT0
VDDT1
VDDT2
VDDT3
VDDT4
VDDT5
VDDT6
VDDT7
GNDT0
GNDT1
GNDT2
GNDT3
GNDT4
GNDT5
GNDT6
GNDT7
VDDD
VDDA
GNDD
GNDA
IC
Type
O
High-Z
I
Pull-up
-
-
-
-
-
-
O
Pin No.
TQFP144 PBGA160
Description
TDO: JTAG Test Data Output
98
F13
This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on the fall-
ing edges of TCK. TDO is a high-Z output signal. It is active only when scanning of data is out. This pin
should be left float when unused.
TDI: JTAG Test Data Input
99 F12 This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and it can be left open.
Power Supplies and Grounds
17
92
G1
G14
3.3 V I/O Power Supply
18
91
G4
G11
I/O GND
44 N4, P4
53 L4, M4
56 L11, M11 3.3 V/5 V Power Supply for Transmitter Driver
65 N11, P11 All VDDT pins must be connected to 3.3 V or all VDDT must be connected to 5 V. It is not allowed to leave
116 A11, B11 any of the VDDT pins open (not-connected) even if the channel is not used.
125 C11, D11 For T1 applications, only 5 V VDDT is supported.
128 C4, D4
137 A4, B4
47 N6, P6
50 L6, M6
59 L9, M9
62
119
N9, P9
A9, B9
Analog GND for Transmitter Driver
122 C9, D9
131 C6, D6
134 A6, B6
19
90
H1
H14
3.3 V Digital/Analog Core Power Supply
20
89
H4
H11
Digital/Analog Core GND
Others
93 G13 IC: Internal Connection
94 H13 Internal use. Leave it float for normal operation.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2048S.PDF ] | |
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