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PDF IDT82V2048L Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2048L | |
| Descripción | OCTAL T1/E1 SHORT HAUL ANALOG FRONT END | |
| Fabricantes | IDT | |
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OCTAL T1/E1 SHORT HAUL
ANALOG FRONT END
IDT82V2048L
FEATURES
! Octal T1/E1 short haul analog front end which supports 100 Ω
T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω E1 coaxial
applications
! Built-in transmit pre-equalization meets G.703 & T1.102
! Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
! ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
! Low impedance transmit drivers with high-Z
! Selectable hardware and parallel/serial host interface
FUNCTIONAL BLOCK DIAGRAM
! Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
! JTAG boundary scan for board test
! 3.3 V supply with 5 V tolerant I/O
! Low power consumption
! Operating temperature range: -40°C to +85°C
! Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
RTIPn
RRINGn
TTIPn
TRINGn
G.772
Monitor
Slicer
LOS
Detector
Peak
Detector
Line
Driver
Clock
Generator
Waveform
Shaper
Transmit
All Ones
Control Interface
One of Eight Identical Channels
Register
File
JTAG TAP
LOSn
RRCDnPn
RDNn
TCLKn
TDPn
TDNn
VDDIO
VDDT
VDDD
VDDA
Figure-1 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
July, 2005
DSC-6527/1
1 page  
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
TDP0
TDP1
TDP2
TDP3
TDP4
TDP5
TDP6
TDP7
TDN0
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
RDP0
RDP1
RDP2
RDP3
RDP4
RDP5
RDP6
RDP7
RDN0
RDN1
RDN2
RDN3
RDN4
RDN5
RDN6
RDN7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Type
I
I
O
High
Imped-
ance
O
High
Imped-
ance
Pin No.
TQFP144 PBGA160
Description
Transmit and Receive Digital Data Interface
37 N2
30 L2
80 L13
73 N13
108 B13 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
101 D13 The NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are
8 D2 active high and are sampled on the falling edges of TCLKn.
1 B2
TDPn
TDNn
Output Pulse
38 N3
31 L3
79 L12
72 N12
0
0
1
1
0 Space
1 Negative Pulse
0 Positive Pulse
1 Space
109 B12
102 D12
7 D3
144 B3
36 N1
29
81
74
107
100
9
L1
L14
N14
B14
D14
D1
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as Table-2
System Interface Configuration.
2 B1
40 P2
33 M2
77 M13
70 P13
111 A13
104 C13
5 C2 RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
142 A2 These pins output the raw RZ sliced data. The active polarity of RDPn/RDNn is determined by pin CLKE.
When pin CLKE is low, RDPn/RDNn is active low. When pin CLKE is high, RPDn/RDNn is active high.
41 P3 RDPn/RDNn will remain active during LOS. RDPn/RDNn is set into high impedance when the correspond-
34 M3 ing receiver is powered down.
76 M12
69 P12
112 A12
105 C12
4 C3
141 A3
39 P1
32 M1
78 M14 RCn: Receive Pulse for Channel 0~7
71 P14 RCn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock
110 A14 is recovered from the signal on RCn. If receiver n is powered down, the corresponding RCn will be in high
103 C14 impedance.
6 C1
143 A1
5
5 Page 
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
2 FUNCTIONAL DESCRIPTION
2.1 OVERVIEW
The IDT82V2048L is a fully integrated octal short-haul analog front
end (AFE), which contains eight transmit and receive channels for use in
either T1 or E1 applications. The raw sliced data (no retiming) is output
to the system. Transmit equalization is implemented with low-impedance
output drivers that provide shaped waveforms to the transformer, guar-
anteeing template conformance. Moreover, testing functions, such as
JTAG boundary scan is provided. The device is optimized for flexible
software control through a serial or parallel host mode interface. Hard-
ware control is also available. Figure-1 on page 1 shows one of the eight
identical channels operation.
2.2 T1/E1 MODE SELECTION
T1/E1 mode selection configures the device globally. In Hardware
control Mode, the template selection pins TS[2:0], determine whether
the operation mode is T1 or E1 (see Table-5 on page 14). In Software
Mode, the register TS determines whether the operation mode is T1 or
E1.
2.2.1 SYSTEM INTERFACE
The system interface of each channel operates in Dual Rail Mode
with data recovery, that is, with raw data slicing only and without clock
recovery.
The Dual Rail interface consist of TDPn1, TDNn, TCLKn, RDPn,
RDNn and RCn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface. The interface of the AFE is
shown in Figure-4. Pin RDPn and RDNn, are raw RZ slice outputs and
internally connected to an XOR which is fed to the RCn output for
external clock recovery applications.
2.2.1.1 SYSTEM INTERFACE CONFIGURATION
For normal transmit and receive operation, the device is configured
as follows:
In host mode, MCLK can be either clocked or pulled high. If MCLK is
pulled high, TCLK1 has to be provided for proper device operation. In
addition, register e-AFE2 has to be set to ‘FFH’ to ensure proper device
operation. See Expanded Register Description on page 28 for details.
In hardware mode, MCLK has to be pulled high and TCLK1 has to be
provided for proper device operation.
Depending on the state of TCLK1 and TCLKn, the transmitter will
Transmit All Ones (TAOS), will go into power down, or will go into high
impedance.
The status of TCLK1 and TCLKn has no effect on the receive paths.
By setting MCLK low, all the receive paths are powered down.
Table-2 summarizes the different combinations between MCLK and
TCLKn.
1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels.
2. The first letter ‘e-’ indicates expanded register.
11
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| PDF Descargar | [ Datasheet IDT82V2048L.PDF ] | |
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