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PDF TC51832PL-85 Data sheet ( Hoja de datos )
| Número de pieza | TC51832PL-85 | |
| Descripción | CMOS PSEUDO STATIC RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MOS MEMORY PRODUCT
32,768 WORD X 8 CMOS PSEUDO STATIC RAM
SILICON MONOLITHIC
SILICON GATE CMOS
TC51832P~85, TC51832P~10
TC51832PL-12
IOESCR! PTImll
The TCSl832PL is a 2S6K bit high speed CNOS pseudo static RAH organized as 32,768
tvords by 8 bits. The TCS1832PL utilized one transistor dynamic cemory cell tvith C~[OS
peripheral circuit to provide large capacity, high speed and low power features. System
oriented features include single power supply of 5VtlO% torelance. The OE/RFSH input
allot·;s ttoJO types of refresh operation - auto refresh and self refresh. The TC5l832PL
also features static WI like write function that the input data iSHritten into the
memory cell at the rising edge of R/W, thus being easy to interface Hith microprocessor.
The TC5l832PL is a pin-compatible tvith 256K bit C:-105 static RAN - TC55257P and is moulded
a standard 0.6 inch width plastic DIP.
IFEil.TURESj
------• Organization: 32,768 Hord 8 bit
• Fast Access Time and Cycle Time
1TC51832PL-85 TC51832PL-I0
tCEA CE Access Time 35ns
lOOns
tOEA OE Access Time 35ns
40ns
tRC Cycle Tir:1e
135ns
160ns
TC51832PL-12
120ns
50ns
190ns
• All inputs and outputs: TTL Com-
patible
• Low POHer Dissipation
Operating
303mW(TC51332PL-8S)
248mW(TCS1832PL-lO)
220mW(TC5l832PL-12)
Standby
1.lmW
• Single Power Supply: SV!lO%
• Static P~[ like ~"rite Function
Self Refresh: 1.lmW
• Two types of Refresh Operation
Capability
IPIN CONNECTIONi
(TOP VIEW)
Auto Refresh
Self Refresh
• Pin compatible with 256K bit c~ros
Al4 Static TAN TCS52S7P
Al2
A7
A6 A8
A5 A9
A4 All
IBLOCK DIAGRAMi
A3 OE/RFSH
A2
Al
AO
1/01
1/02
1/03
I)ND
IPIN NAMESi
CE
1/08
1/07
1/06
1/05
1/04
A14-A8 7
7 COLUMN
--------~I DECODER
ro
o
~
I
rl
o
~
AO tVAl4
R/'"
Address Inputs
Read/Write Control
Input
OE/RFSH
Output Enable/Refresh
Input
CE Chip Enable Input
~/Ol tV 1/08 Data Input/Output
VDn Power (+SV)
GND Ground
~~--=4
_
~
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_-
J
- 8-117-
'.
1 page  
TC51832P~85, TC51832P~10
TC51832PL-12
:iOTES:
1) Stresses greater than those listed under "Absolute ~faximum Ratings" may C3.use
permanent damage to the device.
2) All volt3.ges are reference to G~ID.
3) 1000 depend on cycle rate.
4) 1000 depend on output loading. Specified value are obtained with the output
open.
5) An initial pause of lms ~vith high CE and high OE/RESH is required after pm.:er-
up before proper d~vice operation is achieved.
6) ~C measurements 3.ssume tT=5ns.
7) VIH(min.) and VIL(max.) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIH and VIL'
'3) ~'ieasured ~.Jith a load equivalent to 2 TTL loads and 100pF.
9) The OE/RFSH input operates as the output enable input(OE) and r~fresh control
input(RFSH) under the condition of that CE=VIL and CE=VIH, respectively.
10) tCHZ, tOHZ, ttmz define the time at ~-lhich the output achieves the open circuit
condition and is not reference to output voltage levels.
11) In ~rrite cycles, the input data is latched at the earlier of R/tJ or CE rising
edge. Therefore the input data must be valid during set-up time (tOStJ, tOSC)
and hold time (tOHW, tOHC).
1.2) All address are latched at the falling edge of CEo Therefore must be valid
during tASC and tARC.
13) Two refresh operation - auto refresh and self refresh are determind by the
OE/RFSa pulse \vidth under the condition of CE=VIH'
Auto refresh: OE/RFSH pulse \vidth ;; tFAP (max.)
Self refresh: OE/RFSH pulse width ~ tFAS (min.)
The follmving timing parameter must, be kept before device proper operatio is
achieved after refresh.
Auto refresh: tFCE and tFSR
Self refresh: tFRS
- 8-121 -
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