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PDF TC5563APL-10 Data sheet ( Hoja de datos )
| Número de pieza | TC5563APL-10 | |
| Descripción | CMOS Static RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MOS MEMORY PRODUCT
8,192 WORD X 8 BIT CMOS STATIC RAM TC5563APL-10, TC5563APL-12
SILICON GATE CMOS
TC5563APL-15
PRELIMINARY
DESCRIPTION
The TC5563APL is 65,536 bit static random
access memory organized as 8,192 words by 8 bits
using CMOS technology, and operates from a single
5V supply. Advanced circuit techniques provide both
high speed and low power features with a maximum
operating current of 5mA/MHz and maximum
access time of 1OOns/ 120ns/ 150ns.
When CE2 is a logical low or CE 1 is a logical high.
the device is placed in low power standby mode in
which standby current is 2J.lA typically. The
TC5563APL has three control inputs. Two chip
enables (CE1, CE2) allow for device selection and
data retention control. and an output enable input
(OE) provides fast memory access. Thus the
TC5563APL is suitable for use in various micro-
processor application systems where high speed.
low power. and battery back up are required.
The TC5563APL also features pin compatibility
with the 64k bit EPROM (TMM2764D). RAM and
EPROM are then interchangeable in the same
socket, resulting in flexibility in the definition of the
quantity of RAM versus EPROM in microprocessor
application systems.
The TC5563APL is offered in a dual-in-line 28 pin
0.3 inch width plastic package.
FEATURES
o Low Power Dissipation
27. 5mW/MHz (MAx.) Operating
" Standby Current: 100J.lA (Max.) Ta=70'C
(') Access Time
TC5563APL-l0: lOOns (Max.)
TC5563APL-12: 120ns (Max.)
TC5563APL-15: 150ns (Max.)
o 5V Single Power Supply
PIN CONNECTION (TOP VIEW)
TC5563APL
N.C. 1
VDD
A12
R,/W
Cl!:2
A8
Ag
A4 All
A3 OE
A2
Al
AO
1/01
1/02
1/1)3
Ala
CEI
1/08
1/07
1/06
1/05
OND '--_..::.::.J 1/04
PIN NAMES
64k bit I<;PHOM
TMM2764D
Vpp
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
OND
1
2
3
4
5
6
VCC
POM
N.C.
AS
Ag
All
liE
Ala
CE
07
06
05
04
03
Ao-A'2
R/W
OE
CE,. CE2
1/0,-1/08
Voo
GND
N. C.
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Inputs
Data Input/Output
Power (-+ 5V)
Ground
No Connection
-
(') Power Down Features: CE2, CE 1
o Fully Static Operation
(') Data Retention Supply Voltage: 2.0-5.5V
o Directly TIL Compatible
: All Inputs and Outputs
o Pin Compatible with 2764 type EPROM
o TC5565APL Family (Package Type)
Package Type
600 mil DIP
300 mil DIP
(Slim Package)
Flat Package(SOP)
* )See TC5565APL Technical Date.
DeVice Name
*TC55-65APL
TC5563APL
*TC5565AFL
BLOCK DIAGRAM
8-47 -
1 page  
TC5563AP~10, TC5563AP~12
TC5563APL-15
o WRITE CYCLE 2 (4) (CE 1 Controlled Write)
ADDRESSES
R/W
twc
twp
VIH -
vIL--~~~~~~~~ ~__4 -___t=cw~__~ ~~~~~~~~~~~~
tcw
tODw
VIH -
'VI L - _ _ _ _ _ _ _ _ _ _~ ,'--_ _ _ _ _ _ _---J
«) WRITE CYCLE 3 (4) (CE2 Controlled Write)
ADDHESSES
twc
R/W
DOUT
VIH --
vIL--_ _ _ _ _ _ _ _ _ _ _~
-- 8-51 --
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet TC5563APL-10.PDF ] | |
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