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PDF TC514258Z-10 Data sheet ( Hoja de datos )
| Número de pieza | TC514258Z-10 | |
| Descripción | DRAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC514258Z-10 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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TOSHIBA MOS MEMORY PRODUCT
262,144 WORDS X 4 BIT DYNAMIC RAM
SILICON GATE CMOS
DESCRIPTION
TC514258P/J/Z-85, TC514258P/J/Z-l0
TC514258P/J/Z-12
The TCS142SBP/J/Z is the new generation dynamic RAM organized 262,144 words by 4 bit.
The TCS142SBP/J/Z utilizes TOSHIBA's CMOS Silicon gate process technology as well as ad-
vanced circuit techniques to provide wide operating margins, both internally and to the
system user. MUltiplexed address inputs permit the TCS142SBP/J/Z to be packaged in a
standard 20 pin plastic DIP and 20/26 pin plastic SOJ and 20/19 pin plastic ZIP. The
package size provides high system bit densities and is compatible with widely available
automated testing and insertion equipment. System oriented features include single power
supply of SV±lO% tolerance, direct interfacing capability with high performance logic
families such as Schottky TTL.
FEATURES
• 262,144 words by 4 bit organization
• Fast access time and cycle time
TCS142SBP/J/Z-BS-lO-12
tRAC RAS Access Time
B5ns lOOns l20ns
tAP.
Column Address
Access Time
45ns SOns 60ns
tCAC CS Access Time
30ns 30ns 35ns
tRC Cycle Time
l65ns 190ns 220ns
tsc
Static Column
Hode Cycle Time
SOns S5ns 65ns
• Single power supply of 5V±lO% with a built-in
VBB generator
• Low Power
4l3mW MAX. Operating (TC5l42SBP/J/Z-85)
3SBmW MAX. Operating (TC5l42SBP/J/Z-10)
303mW MAX. Operating (TC5l425BP/J/Z-12)
S.SmW MAX. Standby
• Outputs unlatched at cycle end allows
two-dimensional chip selection
• Read-Modify-Write, CS before RAS refresh,
RAS-only refresh, Hidden refresh and
Static Column Mode capability
• All inputs and outputs TTL complatible
• 512 refresh cycles/Bms
• Package Plastic DIP: TCS142SSP
Plastic SOJ: TC5l42SBJ
Plastic ZIP: TCS142S8Z
PIN CONNECTION (TOP VIEW)
• Plastic DIP • Plastic SOJ
I/02
WRITE
RAS
N.C.
AO
Al
A2
A3
VCC
2
3
4.
5
6
7
S
9
10
AS
A7
A6
A5
A4.
AO
Al
PIN NAt·1ES
AO "'AB
Address Inputs
RAS Row Address Strobe
cs Chip Select
WRITE Read/Write Input
OE Output Enable
1/01", 1/04 Data Input/Output
VCC Power (+5V)
VSS Ground
N.C. No Connection
Plastic ZIP
OE
1/03
-.,
..lJ
~]
r-
~?
1m
Vss
-:-~:
L4
[.6
1/04.
1/01
1/02
RAe
AO
7-
:~
,..
U!
iiUTi
--~~f~
r-
g.,f
Al
A2 :l: 1':-
Vec
.5-; t,.!:4 A3
:~ :!.6 A4
A5 7, ,--
~, :!.8 A6
A7 9! ,...
-'" ~9 AS
AO
Al
A2
A3
A4.
AS
A6
BLOCK DIAGRAr~
I/O 1 I/02 I/03 I/04
-A-157 -
1 page  
TC514258P/ J/Z-85, TC514258P/ J/Z-l 0
TC514258P/J/Z-]2
CAPACITANCE (Vcc=5V±10%, f=lMHz, Ta=O IV 70°C)
SYMBOL
PARAMETER
CII Input Capacitance (AO IV Aa)
CI2 Input Capacitance (RAS, CS, WRITE, OE)
Co Output Capacitance (1/01 '" 1/04)
MIN. MAX. UNIT
-5
- 7 pF
-7
,NOTES:
1. Stresses greater than those listed under t'Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltage are referenced to VSS.
3. Iccl, Icc3, Icc4, Icc6 depend on cycle rate.
4. Iccl, Icc4 depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200~s is required after power-up followed by 8 RAS cycles
before proper device operation is achieved. In case of using internal refresh
counter, a minimum of 8 CS Before RAS initialization cycles instead of a RAS
cycles are required.
6. AC measurements assume tT=5ns.
7. VIH(min.) and VIL(max.) are reference levels for measuring timing of input
signals.
8. Measured with a load equivalent to 2 TTL loads and 10OpF.
9. tOFF(max.) and tOEz(max.) define the time at which the output achieves the open
circuit condition and is not referenced to output voltage levels.
10. Either tRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CS leading edge in early write cycles and to
WRITE leading edge in Read-Modify-Hrite cycles.
12. tws, tWH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are
included the data sheet as electrical characteristics only. If tws~twS(min.), the
cycle is an early write cycle and the data out pin will remain open circuit (high
impedance) through the entire cycle; If tRWD~tRWD(min.), tCWD~tCWD(min.) and
tAWD~tAWD(min.), the cycle is a Read-Modify-Write cycle and the data out will con-
tain data read from the selected cell: If neither of the above sets of conditions
is satisfied, the condition of the data out (at access time) is ind~terminate.
13. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met.
tRCD(max.) is specified as a reference point only: If'tRCD is greater than the
specified tRCD(max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAD(max.) limit insures that tRAC(max.) can be met.
tRAD(max.) is specified as a reference point only: If tRAD is greater than the
specified tRAD(max.) limit, then access time is controlled by tAA.
15. Operation within the tLWAD(max.) limit insures that tALW(max.) can be met. tLWAD
(max.) is specified as a reference point only: If tLWAD is greater than the speci-
fied tLWAD(max.) limit, then access time is controlled exclusively by tAA.
16. tAH is the condition to latch column address when RAS has rised up.
-A-161 -
5 Page 
TC514258P/J/Z-85, TC514258P/J/Z-l0
TC514258P/J/Z-12
STATIC COLUMN MODE READ/WRITE MIXED CYCLE
AO-AS
COLUMN
ADDRESS
COLUMN
ADDRESS
twn
tcWD
tAHLW
I/Ol-I/04r VVOH
VVOL
(READ)
(WRITE)
(READ)
~ :"H"orIlL"
- A-167-
11 Page | ||
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| PDF Descargar | [ Datasheet TC514258Z-10.PDF ] | |
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