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TC514258P-85 fiches techniques PDF

Toshiba - DRAM

Numéro de référence TC514258P-85
Description DRAM
Fabricant Toshiba 
Logo Toshiba 





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TC514258P-85 fiche technique
TOSHIBA MOS MEMORY PRODUCT
262,144 WORDS X 4 BIT DYNAMIC RAM
SILICON GATE CMOS
DESCRIPTION
TC514258P/J/Z-85, TC514258P/J/Z-l0
TC514258P/J/Z-12
The TCS142SBP/J/Z is the new generation dynamic RAM organized 262,144 words by 4 bit.
The TCS142SBP/J/Z utilizes TOSHIBA's CMOS Silicon gate process technology as well as ad-
vanced circuit techniques to provide wide operating margins, both internally and to the
system user. MUltiplexed address inputs permit the TCS142SBP/J/Z to be packaged in a
standard 20 pin plastic DIP and 20/26 pin plastic SOJ and 20/19 pin plastic ZIP. The
package size provides high system bit densities and is compatible with widely available
automated testing and insertion equipment. System oriented features include single power
supply of SV±lO% tolerance, direct interfacing capability with high performance logic
families such as Schottky TTL.
FEATURES
• 262,144 words by 4 bit organization
• Fast access time and cycle time
TCS142SBP/J/Z-BS-lO-12
tRAC RAS Access Time
B5ns lOOns l20ns
tAP.
Column Address
Access Time
45ns SOns 60ns
tCAC CS Access Time
30ns 30ns 35ns
tRC Cycle Time
l65ns 190ns 220ns
tsc
Static Column
Hode Cycle Time
SOns S5ns 65ns
• Single power supply of 5V±lO% with a built-in
VBB generator
• Low Power
4l3mW MAX. Operating (TC5l42SBP/J/Z-85)
3SBmW MAX. Operating (TC5l42SBP/J/Z-10)
303mW MAX. Operating (TC5l425BP/J/Z-12)
S.SmW MAX. Standby
• Outputs unlatched at cycle end allows
two-dimensional chip selection
• Read-Modify-Write, CS before RAS refresh,
RAS-only refresh, Hidden refresh and
Static Column Mode capability
• All inputs and outputs TTL complatible
• 512 refresh cycles/Bms
• Package Plastic DIP: TCS142SSP
Plastic SOJ: TC5l42SBJ
Plastic ZIP: TCS142S8Z
PIN CONNECTION (TOP VIEW)
• Plastic DIP • Plastic SOJ
I/02
WRITE
RAS
N.C.
AO
Al
A2
A3
VCC
2
3
4.
5
6
7
S
9
10
AS
A7
A6
A5
A4.
AO
Al
PIN NAt·1ES
AO "'AB
Address Inputs
RAS Row Address Strobe
cs Chip Select
WRITE Read/Write Input
OE Output Enable
1/01", 1/04 Data Input/Output
VCC Power (+5V)
VSS Ground
N.C. No Connection
Plastic ZIP
OE
1/03
-.,
..lJ
~]
r-
~?
1m
Vss
-:-~:
L4
[.6
1/04.
1/01
1/02
RAe
AO
7-
:~
,..
U!
iiUTi
--~~f~
r-
g.,f
Al
A2 :l: 1':-
Vec
.5-; t,.!:4 A3
:~ :!.6 A4
A5 7, ,--
~, :!.8 A6
A7 9! ,...
-'" ~9 AS
AO
Al
A2
A3
A4.
AS
A6
BLOCK DIAGRAr~
I/O 1 I/02 I/03 I/04
-A-157 -

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