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PDF TC511002J-12 Data sheet ( Hoja de datos )
| Número de pieza | TC511002J-12 | |
| Descripción | DRAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MOS MEMORY PRODUCT
1,048,576 WORDS X 1 BIT DYNAMIC RAM
SILICON GATE CMOS
TC511002P/J/Z-85, TC511002P/J/Z-l0
TC511002P/J/Z-12
DESCRIPTION
The TC5ll002P/J/Z is the new generation dynamic RA}! organized 1,048,576 words by 1
bit. The TC5ll002P/J/Z utilizes TOSHIBA's CXOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the
system user. Multiplexed address inputs permit the TC5ll002P/J/Z to be packaged in a
standard 18 pin plastic DIP,.26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package
size provides system bit densities and is compatible with ~videly available automated test-
ing and insertion equipment. System oriented features include single power supply of
5V±10% tolerance, direct interfacing capability with high performance logic families such
as Schottky TTL. "Test Mode" function is implemented from Revision C.
FEATURES
• 1,048,576 words by 1 bit organization
• Fast access time and cycle time
TC5ll002P/J/Z-85-l0-l2
tp~c RAS Access Time
85ns lOOns l20ns
tM
Column Address
Access Time
45ns 50ns 60ns
tCAC CS Access Time
25ns 25ns 30ns
tRC Cycle Time
l65ns 190ns 220ns
tsc
Static Column
Mode Cycle Time
50ns 55ns 65ns
• Single power supply of 5V±10% with a built-in
VBB generator
PIN CONNECTION CTOP VIEW)
Plastic DIP Plastic SOJ Plastic ZIP
• Low Power
385mt-l MAX. Operating (TC5ll002P / J /Z-85)
330mt-l MAX. Operating (TC5ll002P / J /Z-lO)
275mt-l HAX. Operating (TC5ll002P / J /Z-12)
5 . 5mW ~1A.,{. Standby
• Output unlatched at cycle end allows
t';vo-dimensional chip sel(':!tion
• Common I/O capability
• Read-Modify-Hrite, CS before p~s refresh,
RAS-only refresh, Hidden refresh, Static
Column Mode and Test ~~de capability.
• All inputs and output TTL compatible
• 512 refresh cycles/8ms
• Package
Plastic DIP: TC5ll002P
Plastic SOJ: TC5ll002J
Plastic-ZIP: TC5ll002Z
Vss
DIN
DOUT WRITE
"C'S' RAS
A9
TF
N.C.
AO A8
A7 AO
A6 A1
A2
A5 A3
A4. VCC
PIN r'IM~ES
AO "'A9
RAS
DIN
DOUT
CS
WRITE
VCC
VSS
TF
N.C.
Address Inputs
Row Address Strobe
Data In
Data Out
Chip Select Input
Read/Write Input
Power (+5V)
Ground
Test Function
No Connection
Vss
DOUT
TI"S'
N.C.
A9
A8
A7
A6
A5
A4.
BLOCK 0IAGRn.r·1
AO
A1
A2
A3
A4-
A5
AS
A7
A8
A9
-A-125-
1 page  
TC511002P/J/Z-85, TC511002P/J/Z-l0
TC511002P/J/Z-12
C'APACITANCE (VCC=5V±10% t f=lMHz t Ta=O '" 70°C)
SYMBOL
Cl1
CI2
Co
PARAMETER
Input Capacitance (AO ",A9, DIN)
Input Capacitance (RAS, CS, WRITE, TF)
Output Capacitance (DOUT)
MIN. MAX. UNIT
-5
- 7 pF
-7
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are refere~ced to VSS.
3. ICC1, ICC3, ICC4, ICC6 depend on cycle rate.
4. ICC1' ICC4 depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200 ~s is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved.
In case of using internal refresh counter, a minimum of 8 CSBefore RAS intializa-
tion cycles instead of 8 RAS cycles are required.
6. AC measurements assume tT=5ns.
7. VIR(min.) and VIL(max.) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIR and VIL.
8. Measured with a load equivalent to 2 TTL loads and 100pF.
9. tOFF(max.) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
10. EithertRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CS leading edge in early write cycles and to
WRITE leading edge in read-write cycles.
12. tws, tWE, tRWD, tCWD and tAWD are not restrictive operating parameters. They are
included in the data sheet as e1ecteical characteristics only. If tws ~tws(min.)
and ttm ~ ttm(min.), the cycle is an early write cycle and data out pin will remain
open circuit (high impedance) throughout the entire cycles; If tRHD ~tRWD(min.),
tCWD ~ tCt-ID (min.) and tAtID ~ tAWD (min. ), the cycle is a read-write cycle and the
data out will contain data read from the selected cell: If neither or the above
sets of conditions is satisfied, the condition of the data out (at access time)
is indeterminate.
13. Operation within the tRCo(max.) limit insures that tRAc(max.) can be met. tRCD
(max.) is specified as a reference point only: If tRCO is greater than the spec-
ilied tRCD(max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAD(max.) limit insures that tRAC(max.) can be met.
tRAo(max.) is specified as a reference point only: If tRAD is greater than the
specified tRAD(max.) limit, then access time is controlled exclusively by tAA.
15. Operation within the tLWAD(max.) limit insures that tALW(max.) can be met. tLWAD
(max.) is specified as a reference point only: If tLWAD is greater than the spec-
ified tLWAD(max.) limit, then access time is controlled exclusively by tAA.
16. tAH is the condition to latch column address when RAS has rised up.
-A-129-
5 Page 
HIDDEN REFRESH CYCLE (READ)
_ VIR-
RAS
VIL -
TC511002P/J/Z-85, TC511002P/J/Z-l0
TC511002P/J/Z-12
tCRP
AO-A9
VIL -
7mrrs VIH-
T/IL - ...........................~
'IOH - _ _ _ _ _~I_~', . . . - - - - - - - - - - - . > - -_ _ _ _ __
Dour
._
VALID DATA
VOL -
tcLZ I I
HIDDEN REFRESH CYCLE (t.ffiITE)
~ IIHllorllL"
~TOTE: "TF" pin should be connected to VIL level or open, if "Test
:lode" is not used.
-A-135-
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| PDF Descargar | [ Datasheet TC511002J-12.PDF ] | |
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