CD4050BMS Datasheet PDF - Intersil Corporation
| Part Number | CD4050BMS | |
| Description | CMOS Hex Buffer/Converter | |
| Manufacturers | Intersil Corporation | |
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CD4050BMS
December 1992
File Number 3193
CMOS Hex Buffer/Converter
The CD4050BMS is an non-inverting hex buffer and features
logic level conversion using only one supply voltage (VCC).
The input signal high level (VIH) can exceed the VCC supply
voltage when this device is used for logic level conversions.
This device is intended for use as CMOS to DTL/TTL
converters and can drive directly two DTL/TTL loads. (VCC
= 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.
The CD4050BMS is designated as replacement for
CD4010B. Because the CD4050BMS requires only one
power supply, it is preferred over the CD4010B and should
be used in place of the CD4010B in all inverter, current
driver, or logic level conversion applications. In these appli-
cations the CD4050BMS is pin compatible with the
CD4010B, and can be substituted for this device in existing
as well as in new designs. Terminal No. 16 is not connected
internally on the CD4050BMS, therefore, connection to this
terminal is of no consequence to circuit operation. For appli-
cations not requiring high sink current or voltage conversion,
the CD4069UB Hex Inverter is recommended.
The CD4050BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP
H1E
Ceramic Flatpack H3X
Features
• High Voltage Type (20V Rating)
• Non-Inverting Type
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-to-Low Logic Level Converter
Pinout
CD4050BMS
TOP VIEW
VCC 1
G=A 2
A3
H=B 4
B5
I=C 6
C7
VSS 8
16 NC
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9D
Functional Diagram
3
A
5
B
7
C
VCC
VSS
1
8
NC = 13
NC = 16
9
D
11
E
14
F
2
G=A
4
H=B
6
I=C
10
J=D
12
K=E
15
L=F
Schematic Diagram
VCC
R
IN
PP
OUT
NN
VSS
FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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CD4050BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parametric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
POST-IRRAD
1, 7, 9
Table 4
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 (Note 1) 2, 4, 6, 10, 12, 13, 15 3, 5, 7-9, 11-14
1, 16
Static Burn-In 2 (Note 1) 2, 4, 6, 10, 12, 13, 15
8 1, 3, 5, 7, 9, 11, 14, 16
Dynamic Burn-In (Note 3)
13
8
1, 16
2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14
Irradiation (Note 2)
2, 4, 6, 10, 12, 13, 15, 16
8
1, 3, 5, 7, 9, 11, 14
NOTES:
1. Each pin except pin 1, pin 16, and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except pin 1, pin 16, and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
3. Each pin except pin 1, pin 16, and GND will have a series resistor of 4.75K ± 5%, VDD = 10V ± 0.5V
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VCC) = 5V
5
4
MINIMUM
3
MAXIMUM
2
1
0
12 3
INPUT VOLTAGE (VI) (V)
4
FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
70
15V 10V
60
50
40
30
GATE-TO-SOURCE VOLTAGE (VGS) = 5V
20
10
0 12 34 5 67 8
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
4-5
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