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PDF CD4046BC Data sheet ( Hoja de datos )
| Número de pieza | CD4046BC | |
| Descripción | Micropower Phase-Locked Loop | |
| Fabricantes | Fairchild Semiconductor | |
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October 1987
Revised March 2002
CD4046BC
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) con-
sists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators. The two phase comparators have a common
signal input and a common comparator input. The signal
input can be directly coupled for a large voltage signal, or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digi-
tal error signal (phase comp. I Out) and maintains 90°
phase shifts at the VCO center frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input frequencies that are close to har-
monics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase comp. II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0° phase shift between signal
input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCOIN input, and the capacitor and resis-
tors connected to pin C1A, C1B, R1 and R2.
The source follower output of the VCOIN (demodulator Out)
is used with an external resistor of 10 kΩ or more.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode is provided for power supply regulation, if
necessary.
Features
s Wide supply voltage range: 3.0V to 18V
s Low dynamic power consumption: 70 µW (typ.)
at fo = 10 kHz, VDD = 5V
s VCO frequency: 1.3 MHz (typ.) at VDD = 10V
s Low frequency drift: 0.06%/°C at VDD = 10V with
temperature
s High VCO linearity: 1% (typ.)
Applications
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Ordering Code:
Order Number Package Number
Package Description
CD4046BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4046BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS005968
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
VCOIN−
VDEM
Offset Voltage
Linearity
RS ≥ 10 kΩ, VDD = 5V
RS ≥ 10 kΩ, VDD = 10V
RS ≥ 50 kΩ, VDD = 15V
RS ≥ 50 kΩ
ZENER DIODE
VCOIN = 2.5V ± 0.3V, VDD = 5V
VCOIN = 5V ± 2.5V, VDD = 10V
VCOIN = 7.5V ± 5V, VDD = 15V
VZ Zener Diode Voltage
IZ = 50 µA
RZ Zener Dynamic Resistance
IZ = 1 mA
Note 5: AC Parameters are guaranteed by DC correlated testing.
Phase Comparator State Diagrams
Min
Typ
Max
Units
1.50
2.2
1.50
2.2
V
1.50
2.2
0.1
0.6 %
0.8
6.3 7.0 7.7
100
V
Ω
FIGURE 2.
5 www.fairchildsemi.com
5 Page 
Design Information
This information is a guide for approximating the value of
external components for the CD4046B in a phase-locked-
loop system. The selected external components must be
within the following ranges: R1, R2 ≥ 10 kΩ, RS ≥ 10 kΩ,
C1 ≥ 50 pF.
In addition to the given design information, refer to Figure
5, Figure 6, Figure 7 for R1, R2 and C1 component selec-
tions.
Characteristics
VCO Frequency
Using Phase Comparator I
VCO Without Offset
VCO With Offset
R2 = ∞
Using Phase Comparator II
VCO Without Offset
VCO With Offset
R2 = ∞
For No Signal Input
Frequency Lock
Range, 2 fL
Frequency Capture
Range, 2 fC
VCO in PLL system will adjust
VCO in PLL system will adjust to
to center frequency, fo
lowest operating frequency, fmin
2 fL = full VCO frequency range
2 fL = fmax − fmin
Loop Filter Component
Selection
For 2 fC, see Ref.
Phase Angle Between
Single and Comparator
Locks on Harmonics
of Center Frequency
Signal Input Noise
Rejection
90° at center frequency (fo), approximating
0° and 180° at ends of lock range (2 fL)
Yes
High
fC = fL
Always 0° in lock
No
Low
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CD4046BC.PDF ] | |
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