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Número de pieza FDS8958B
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FDS8958B
Dual N & P-Channel PowerTrench® MOSFET
Q1-N-Channel: 30 V, 6.4 A, 26 mQ2-P-Channel: -30 V, -4.5 A, 51 m
November 2013
Features
Q1: N-Channel
„ Max rDS(on) = 26 mat VGS = 10 V, ID = 6.4 A
„ Max rDS(on) = 39 mat VGS = 4.5 V, ID = 5.2 A
Q2: P-Channel
„ Max rDS(on) = 51 mat VGS = -10 V, ID = -4.5 A
„ Max rDS(on) = 80 mat VGS = -4.5 V, ID = -3.3 A
„ HBM ESD protection level > 3.5 kV (Note 3)
General Description
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild Semiconductor's
advanced PowerTrench® process th at has been especially
tailored to minimize on-state resistan ce and yet maintain
superior switching performance.
These devices are well suite d for low voltage and battery
powered applications where low in-line power loss and fast
switching are required.
Application
„ RoHS Compliant
„ DC-DC Conversion
„ BLU and motor drive inverter
D2
D1
D1
D2
Pin 1
G2
S2
G1
S1
D2 5
D2 6
D1 7
D1 8
Q2
Q1
4 G2
3 S2
2 G1
1 S1
SO-8
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
EAS
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
Single Pulse Avalanche Energy
Operating and Storage Junction Temperature Range
TA = 25 °C
TA = 25 °C
TA = 25 °C
(Note 1a)
(Note 1b)
(Note 4)
Thermal Characteristics
Q1 Q2
30 -30
±20 ±25
6.4 -4.5
30 -30
2.0
1.6
0.9
18 5
-55 to +150
Units
V
V
A
W
mJ
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1)
(Note 1a)
40
78
°C/W
Device Marking
FDS8958B
Device
FDS8958B
Package
SO-8
Reel Size
13 ”
Tape Width
12 mm
Quantity
2500 units
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
1
www.fairchildsemi.com

1 page




FDS8958B pdf
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 6.4 A
8
VDD = 10 V
6
VDD = 15 V
4
VDD = 20 V
2
0
0 2 4 6 8 10
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
1000
Ciss
100 Coss
Crss
f = 1 MHz
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
9
8
7
6
5
4 TJ = 25 oC
3
2
TJ = 125 oC
1
0.001
0.01 0.1
1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
500
100
100
THIS AREA IS
LIMITED BY rDS(on)
10
0.1 ms
1
0.1
0.01
0.01
SINGLE PULSE
TJ = MAX RATED
RθJA = 135 oC/W
TA = 25 oC
1 ms
10 ms
100 ms
1s
10 s
DC
0.1 1 10
VDS, DRAIN to SOURCE VOLTAGE (V)
100
Figure 10. Forward Bias Safe
Operating Area
100 VGS = 10 V
10
SINGLE PULSE
RθJA = 135 oC/W
TA = 25 oC
1
0.5
10-4
10-3
10-2
10-1
1
10
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
100
1000
©2008 Fairchild Semiconductor Corporation
FDS8958B Rev.C
5
www.fairchildsemi.com

5 Page





FDS8958B arduino
© 2008 Fairchild Semiconductor Corporation
FDS8958B Rev. C
11
www.fairchildsemi.com

11 Page







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