PDF CD4040BC Data sheet ( Hoja de datos )

Número de pieza	CD4040BC
Descripción	14-Stage/ 12-Stage Ripple Carry Binary Counters
Fabricantes	National Semiconductor
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No Preview Available ! October 1987 Revised January 1999 CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary Counters • 14-Stage Ripple Carry Binary Counters General Description The CD4020BC, CD4060BC are 14-stage ripple carry binary counters, and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical “1” at the reset input independent of clock. Features s Wide supply voltage range: 1.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Medium speed operation: 8 MHz typ. at VDD = 10V s Schmitt trigger clock input Ordering Code: Order Number Package Number Package Description CD4020BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4020BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4040BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4040BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4040BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4060BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4060BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC CD4020BC Pin Assignments for DIP, SOIC and SOP CD4040BC Top View Top View © 1999 Fairchild Semiconductor Corporation DS005953.prf www.fairchildsemi.com 1 page AC Electrical Characteristics (Note 4) CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted Symbol Parameter Conditions Min tPHL1, tPLH1 Propagation Delay Time to Q1 VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH Interstage Propagation Delay Time VDD = 5V from Qn to Qn+1 VDD = 10V VDD = 15V tTHL, tTLH Transition Time VDD = 5V VDD = 10V VDD = 15V tWL, tWH Minimum Clock Pulse Width VDD = 5V VDD = 10V VDD = 15V trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Frequency VDD = 5V VDD = 10V VDD = 15V tPHL(R) Reset Propagation Delay VDD = 5V VDD = 10V VDD = 15V tWH(R) Minimum Reset Pulse Width VDD = 5V VDD = 10V VDD = 15V CIN Average Input Capacitance Any Input CPD Power Dissipation Capacitance Note 4: AC Parameters are guaranteed by DC correlated testing. 1.5 4 5 Typ Max Units 250 550 ns 100 210 ns 75 150 ns 150 330 ns 60 125 ns 45 90 ns 100 200 ns 50 100 ns 40 80 ns 125 335 ns 50 125 ns 40 100 ns No Limit ns No Limit ns No Limit ns 4 MHz 10 MHz 12 MHz 200 450 ns 100 210 ns 80 170 ns 200 450 ns 100 210 ns 80 170 ns 5 7.5 pF 50 pF 5 www.fairchildsemi.com 5 Page

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