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Número de pieza | FDBL0110N60 | |
Descripción | MOSFET ( Transistor ) | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! FDBL0110N60
N-Channel PowerTrench® MOSFET
60 V, 300 A, 1.1 mΩ
January 2016
Features
Typical RDS(on) = 0.85 mΩ at VGS = 10V, ID = 80 A
Typical Qg(tot) = 170 nC at VGS = 10V, ID = 80 A
UIS Capability
RoHS Compliant
Applications
Industrial Motor Drive
Industrial Power Supply
Industrial Automation
Battery Operated tools
Battery Protection
Solar Inverters
UPS and Energy Inverters
Energy Storage
Load Switch
D
G
S
For current package drawing, please refer to the Fairchild
website at https://www.fairchildsemi.com/evaluate/pack-
age-specifications/packageDetails.ht-
ml?id=PN_PSOFA-008
MOSFET Maximum Ratings TJ = 25°C unless otherwise noted.
Symbol
Parameter
VDSS
VGS
ID
Drain-to-Source Voltage
Gate-to-Source Voltage
Drain Current - Continuous (VGS=10) (Note 1)
Pulsed Drain Current
EAS Single Pulse Avalanche Energy
PD
Power Dissipation
Derate Above 25oC
TJ, TSTG
RθJC
RθJA
Operating and Storage Temperature
Thermal Resistance, Junction to Case
Maximum Thermal Resistance, Junction to Ambient
TC = 25°C
TC = 25°C
(Note 2)
(Note 3)
Ratings
60
±20
300
See Figure 4
1167
429
2.86
-55 to + 175
0.35
43
Units
V
V
A
mJ
W
W/oC
oC
oC/W
oC/W
Notes:
1: Current is limited by bondwire configuration.
2: Starting TJ = 25°C, L = 0.57mH, IAS = 64A, VDD = 40V during inductor charging and VDD = 0V during time in avalanche.
3: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface
presented here is
of the
based
drain pins. RθJC is
on mounting on a 1
guaranteed by design,
in2 pad of 2oz copper.
while
RθJAis
determined
by
the
board
design.
The maximum rating
Package Marking and Ordering Information
Device Marking
FDBL0110N60
Device
FDBL0110N60
Package
MO-299A
-
-
-
©2014 Fairchild Semiconductor Corporation
FDBL0110N60 Rev.1.2
1
www.fairchildsemi.com
1 page 11.58
11.78
9.70
9.90
0.60
0.80
(0.40)
(3.30) (2X)
1
0.60
(0.35)
1.20
7X
8.40
TOP VIEW
8
0.50
0.70
0.70
0.90
(8X)
0.25 C A B
0.20 C
DETAIL "A"
B
10.28
10.48
0.40
0.60
10°
0.60
0.80
0.20 C A B
DETAIL "A"
10.20
5.10
4.45
0.20 C
2.20
2.40
0.10 C
SIDE VIEW
DETAIL "B"
0.40
0.60
C
A
5.19
(7.15) 6.55
6.75
5.89
9.80
10.00
(8.00)
4.73
(2X)
0.20 C A B
1.90
2.10
0.10
2.60 (2X)
3.30 (2X)
3.75
1.20
3X
7.40
7.60
(8.30)
0.65
2X
BOTTOM VIEW
10°
6.64
4.99
2.04
1.46
6.64 0.86
1
0.80
2.95
8.10
2.90
13.28
0.60
2.80
8
1.20
LAND PATTERN
RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-299, ISSUE A, DATED NOVEMBER
2009.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: MKT-PSOF08AREV3
(0.35)
DETAIL "B"
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet FDBL0110N60.PDF ] |
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FDBL0110N60 | MOSFET ( Transistor ) | Fairchild Semiconductor |
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