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PDF FDMD85100 Data sheet ( Hoja de datos )
| Número de pieza | FDMD85100 | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2015
FDMD85100
Dual N-Channel PowerTrench® MOSFET
Q1: 100 V, 48A, 9.9 mΩ Q2: 100 V, 48A, 9.9 mΩ
Features
General Description
Q1: N-Channel
Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A
Max rDS(on) = 16.4 mΩ at VGS = 6 V, ID = 8 A
Q2: N-Channel
Max rDS(on) = 9.9 mΩ at VGS = 10 V, ID = 10.4 A
Max rDS(on) = 16.4 mΩ at VGS = 6 V, ID = 8 A
Ideal for flexible layout in primary side of bridge topology
Termination is Lead-free and RoHS Compliant
100% UIL tested
Kelvin High Side MOSFET drive pin-out capability
This device includes two 100V N-Channel MOSFETs in a dual
Power (5 mm X 6 mm) package. HS source and LS Drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Applications
Synchronous Buck : Primary Switch of Half / Full Bridge
Bonverter for Telecom
Motor Bridge : Primary Switch of Half / Full Bridge Converter
for BLDC Motor
MV POL : 48V Synchronous Buck Switch
Half/Full Bridge Secondary Synchronous Rectification
Top Bottom
Pin 1
D2/S1
D2/S1
D2/S1
S2 G2
G1
GR
G2
D2/S1
D1 D1
D1
GR
G1
Pin 1
Power 5 x 6
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
VGS
ID
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
Drain Current -Continuous
-Pulsed
Parameter
TC = 25 °C
TC = 100 °C
TA = 25 °C
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
D1
D1
(Note 5)
(Note 5)
(Note 4)
(Note 3)
D2/S1
D2/S1
Q1 Q2
100 100
±20 ±20
48 48
30
10.41a
30
10.41b
261 261
294 294
50
2.21a
50
2.21b
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Package Marking and Ordering Information
2.5
551a
2.5
55 1b
°C/W
Device Marking
FDMD85100
Device
FDMD85100
Package
Power 5 x 6
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDMD85100 Rev.1.2
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
10
ID = 10.4 A
8
6
4
VDD = 25 V
VDD = 50 V
VDD = 75 V
2
0
0 4 8 12 16 20 24
Qg, GATE CHARGE (nC)
10000
1000
Ciss
Coss
100
Crss
10
f = 1 MHz
VGS = 0 V
5
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
Figure 7. Gate Charge Characteristics
Figure8. Capacitancevs.Drain
to Source Voltage
100
TJ = 25 oC
10 TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
50
RθJC = 2.5 oC/W
40
VGS = 10 V
30
VGS = 6 V
20
10
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
1000
100
10 μs
10
THIS AREA IS
1 LIMITED BY rDS(on)
SINGLE PULSE
0.1
TJ = MAX RATED
RθJC = 2.5 oC/W
TC = 25 oC
0.01
0.1
1
CURVE BENT TO
MEASURED DATA
10
100 μs
1 ms
10 ms
DC
100 400
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
10000
1000
SINGLE PULSE
RθJC = 2.5 oC/W
TC = 25 oC
100
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
Figure 12. Single Pulse Maximum Power
Dissipation
©2015 Fairchild Semiconductor Corporation
FDMD85100 Rev.1.2
5
www.fairchildsemi.com
5 Page 
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