PDF KSZ8851SNLI Data sheet ( Hoja de datos )

Número de pieza	KSZ8851SNLI
Descripción	Single-Port Ethernet Controller
Fabricantes	Micrel Semiconductor
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No Preview Available ! KSZ8851SNL/SNLI Single-Port Ethernet Controller with SPI Interface Rev. 2.0 General Description The KSZ8851SNL is a single-chip Fast Ethernet controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Serial Peripheral Interface (SPI). The KSZ8851SNL is designed to enable an Ethernet network connectivity with any host micro-controller equipped with SPI interface. The KSZ8851SNL offers the most cost- effective solution for adding high-throughput Ethernet link to traditional embedded systems with SPI interface. The KSZ8851SNL is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, SPI interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851SNL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851SNL, the KSZ8851SNLI is also available (see “Ordering Information” section). LinkMD® Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. The KSZ8851SNL is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V VDD I/O. The device includes an extensive feature set that offers management information base (MIB) counters and a fast SPI interface with clock speed up to 40MHz. The KSZ8851SNL includes unique cable diagnostics feature called LinkMD®. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851SNL supports Hewlett Packard (HP) Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications. Functional Diagram Figure 1. KSZ8851SNL/SNLI Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Magic Packet is a trademark of Advanced Micro Devices, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc. Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 2009 M9999-083109-2.0 1 page Micrel, Inc. KSZ8851SNL/SNLI Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL............................................................. 26 Receive Queue (RXQ) Frame Format ..................................................................................................................... 29 Frame Receiving Path Operation in RXQ ................................................................................................................ 29 Driver Routine for Receive Packet from KSZ8851SNL to Host Processor.............................................................. 30 EEPROM Interface ......................................................................................................................................................... 31 Loopback Support........................................................................................................................................................... 32 Near-end (Remote) Loopback.................................................................................................................................. 32 Far-end (Local) Loopback ........................................................................................................................................ 32 SPI Interface to I/O Registers............................................................................................................................................. 33 I/O Registers................................................................................................................................................................... 33 Internal I/O Registers Space Mapping............................................................................................................................ 34 Register Map: MAC, PHY and QMU................................................................................................................................... 40 Bit Type Definition........................................................................................................................................................... 40 0x00 – 0x07: Reserved................................................................................................................................................... 40 Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 40 0x0A – 0x0F: Reserved .................................................................................................................................................. 40 Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 40 Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 41 Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 41 Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 41 0x16 – 0x1F: Reserved .................................................................................................................................................. 41 On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 41 EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 42 Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 42 Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 43 0x28 – 0x29: Reserved................................................................................................................................................... 43 Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 43 0x2C – 0x2F: Reserved .................................................................................................................................................. 43 Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 43 Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 44 Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 44 Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 44 Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 44 Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 44 0x3C – 0x3F: Reserved .................................................................................................................................................. 45 Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 45 Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 45 Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 45 Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 45 Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 45 Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 45 0x4C – 0x4F: Reserved .................................................................................................................................................. 46 Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 46 Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 46 Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 46 August 2009 5 M9999-083109-2.0 5 Page Micrel, Inc. KSZ8851SNL/SNLI Pin Description Pin Number 1 Pin Name LED0 2 PME 3 INTRN 4 DGND 5 VDD_CO1.8 6 EED_IO 7 EESK 8 AGND 9 VDD_A1.8 10 EECS 11 RXP 12 RXM 13 AGND 14 TXP 15 TXM 16 VDD_A3.3 17 ISET 18 AGND 19 RSTN Type Opu Opu Opu Gnd P Ipd/O Opd Gnd P Opd I/O I/O Gnd I/O I/O P O Gnd Ipu Pin Function Programmable LED output to indicate PHY activity/status. LED is ON when output is LOW; LED is OFF when output is HIGH. LED indicators1 defined as follows: LED1 (pin 32) LED0 (pin 1) Chip Global Control Register: CGCR bit [9] 0 (Default) 1 100BT ACT LINK/ACT LINK Link (up) = LED On; Activity = LED Blink; Link/Act = LED On/Blink; Speed = LED On (100BASE-T); LED Off (10BASE-T) Power Management Event (default active low) It is asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851SNL. The KSZ8851SNL is requesting the system to wake up from low power mode. Interrupt Not An active low signal to host CPU to indicate an interrupt status bit is set. This pin needs an external 4.7K pull-up resistor. Digital IO ground. 1.8V regulator output . This 1.8V output pin provides power to pins 9 (VDD_A1.8) and 23 (VDD_D1.8) for core VDD supply. If VDD_IO is set for 1.8V then this pin should be left floating, pins 9 (VDDA_1.8) and 23 (VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 25 and 30 (VDD_IO) with appropriate filtering. In/Out Data from/to external EEPROM Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during power-up / reset. See “Strapping Options” section for details. EEPROM Serial Clock A 4μs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip bus speed @ 125 MHz) serial output clock to load configuration data from the serial EEPROM. Analog ground. 1.8V analog power supply from VDD_CO1.8 (pin 5) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 25 and 30 (VDD_IO) with appropriate filtering. EEPROM Chip Select This signal is used to select an external EEPROM device. Physical receive (MDI) or transmit (MDIX) signal (+ differential). Physical receive (MDI) or transmit (MDIX) signal (– differential). Analog ground. Physical transmit (MDI) or receive (MDIX) signal (+ differential). Physical transmit (MDI) or receive (MDIX) signal (– differential). 3.3V analog VDD input power supply with well decoupling capacitors. Set physical transmits output current. Pull-down this pin with a 3.01K 1% resistor to ground. Analog ground. Reset Not. August 2009 11 M9999-083109-2.0 11 Page

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