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PDF AD9135 Data sheet ( Hoja de datos )
| Número de pieza | AD9135 | |
| Descripción | Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converters
AD9135/AD9136
FEATURES
Support input data rate >2 GSPS
Proprietary low spurious and distortion design
SFDR = 82 dBc at dc IF, −9 dBFS
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Selectable 1×, 2×, 4×, or 8× interpolation filter
Low power architecture
Transmit enable function allows extra power saving and
instant control of the output status
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Low power: 1.42 W at 1.6 GSPS full operating conditions
88-lead LFCSP with exposed pad
APPLICATIONS
Wireless communications
3G/4G W-CDMA base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point
Local multipoint distribution service (LMDS) and
multichannel multipoint distribution service (MMDS)
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range
digital-to-analog converters (DACs) that provide a maximum
sample rate of 2800 MSPS, permitting a multicarrier generation
over a very wide bandwidth. The DAC outputs are optimized to
interface seamlessly with the ADRF6720, as well as other analog
quadrature modulators (AQMs) from Analog Devices, Inc. An
optional 3-wire or 4-wire serial port interface (SPI) provides for
programming/readback of many internal parameters. The full-
scale output current can be programmed over a typical range of
13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an
88-lead LFCSP.
TYPICAL APPLICATION CIRCUIT
QUAD MOD
ADRF6720
LPF
SYSREF±
RF OUTPUT
0°/90° PHASE
SHIFTER
LO_IN MOD_SPI
DAC
DAC
AD9135/
AD9136
JESD204B
SYNCOUT0±
SYNCOUT1±
Figure 1.
CLK±
DAC
SPI
PRODUCT HIGHLIGHTS
1. Greater than 2 GHz, ultrawide complex signal bandwidth
enables emerging wideband and multiband wireless
applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
4. Fewer pins for data interface width with a serializer/
deserializer (SERDES) JESD204B eight-lane interface.
5. Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
6. Small package size with 12 mm × 12 mm footprint.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9135/AD9136
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
I/Q Gain Mismatch
Full-Scale Output Current
(IOUTFS)
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Gain DAC Monotonicity
Settling Time
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12
CVDD12
DIGITAL SUPPLY VOLTAGES
SIOVDD33
VTT
DVDD12
SVDD12
IOVDD
POWER CONSUMPTION
1× Interpolation Mode,
JESD Mode 8, 8 SERDES Lanes
AVDD33
PVDD12
CVDD12
SVDD12
DVDD12
SIOVDD33
IOVDD
Test Conditions/Comments
With calibration
With internal reference
Based on a 4 kΩ external resistor
between I120 and GND
To within ±0.5 LSB
1.2 V nominal supply voltage
1.3 V nominal supply voltage
1.2 V nominal supply voltage
1.3 V nominal supply voltage
fDAC = 1.6 GSPS, IF = 40 MHz, PLL on,
digital gain on, inverse sinc on, DAC
full-scale current (IOUTFS) = 20 mA
Includes VTT
AD9135
AD9136
Min Typ
Max Min Typ
Max Unit
11 16 Bits
±0.175
±0.35
±1.0 LSB
±2.0 LSB
−2.5 +2
−0.6
+5.5 −2.5 +2
+0.6 −0.6
+5.5 % FSR
+0.6 % FSR
25.5
13.1
−250
27.0
13.9
0.2
3.0
Guaranteed
20
28.6
14.8
+750
25.5
13.1
−250
27.0
13.9
0.2
3.0
Guaranteed
20
28.6
14.8
+750
mA
mA
mV
MΩ
pF
ns
0.04 0.04 ppm
32 32 ppm/°C
1.2 1.2 V
3.13 3.3
1.14 1.2
1.14 1.2
3.47 3.13 3.3
1.26 1.14 1.2
1.26 1.14 1.2
3.47 V
1.26 V
1.26 V
3.13
1.1
1.14
1.274
1.14
1.274
1.71
3.3
1.2
1.2
1.3
1.2
1.3
1.8
3.47
1.37
1.26
1.326
1.26
1.326
3.47
3.13
1.1
1.14
1.274
1.14
1.274
1.71
3.3
1.2
1.2
1.3
1.2
1.3
1.8
3.47
1.37
1.26
1.326
1.26
1.326
3.47
V
V
V
V
V
V
V
1.42 1.74
1.42 1.74 W
68 73
100 113.4
101 112
554 665
196 224
11 12
36 50
68 73 mA
100 113.4 mA
101 112 mA
554 665 mA
196 224 mA
11 12 mA
36 50 μA
Rev. A | Page 5 of 117
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter
I120 to Ground
SERDINx±, VTT, SYNCOUT1±/
SYNCOUT0±, TXENx
OUTx±
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO,
SDO to Ground
LDO_BYP1
LDO_BYP2
LDO24
Ambient Operating Temperature (TA)
Operating Junction Temperature
Storage Temperature Range
Rating
−0.3 V to AVDD33 + 0.3 V
−0.3 V to SIOVDD33 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
GND − 0.5 V to +2.5 V
−0.3 V to PVDD12 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to SVDD12 + 0.3 V
−0.3 V to PVDD12 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
−40°C to +85°C
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD9135/AD9136
THERMAL RESISTANCE
The exposed pad (EPAD) must be soldered to the ground plane
for the 88-lead LFCSP. The EPAD provides an electrical, thermal,
and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer
JESD51-7 high effective thermal conductivity test board for
leaded surface-mount packages. θJA is obtained in still air
conditions (JESD51-2). Airflow increases heat dissipation,
effectively reducing θJA. θJB is obtained following double-ring
cold plate test conditions (JESD51-8). θJC is obtained with the test
case temperature monitored at the bottom of the exposed pad.
ΨJT and ΨJB are thermal characteristic parameters obtained with
θJA in still air test conditions.
Junction temperature (TJ) can be estimated using the following
equations:
TJ = TT + (ΨJT × P)
or
TJ = TB + (ΨJB × P)
where:
TT is the temperature measured at the top of the package.
P is the total device power dissipation.
TB is the temperature measured at the board.
Table 11. Thermal Resistance
Package
θJA θJB θJC ΨJT ΨJB Unit
88-Lead LFCSP1 22.6 5.59 1.17 0.1 5.22 °C/W
1 The exposed pad must be securely connected to the ground plane.
ESD CAUTION
Rev. A | Page 11 of 117
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9135.PDF ] | |
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