|
|
PDF AD7173-8 Data sheet ( Hoja de datos )
| Número de pieza | AD7173-8 | |
| Descripción | Highly Integrated Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7173-8 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
Low Power, 8-/16-Channel, 31.25 kSPS,
24-Bit, Highly Integrated Sigma-Delta ADC
AD7173-8
FEATURES
APPLICATIONS
Low power, 8-/16-channel, highly integrated multiplexed
analog-to-digital converter (ADC)
Integration
Precision analog input buffers and reference input buffers
2.5 V precision reference (3.5 ppm/°C)
Cross point multiplexer (enable system diagnostic)
Process control: PLC/DCS modules
Voltage, current, temperature, and pressure measurement
Flow meters
Medical and scientific multichannel instrumentation
Seismic instrumentation
Chemical analysis instrumentation: chromatography
8 full differential or 16 single-ended channels
Clock oscillator
GPIO and GPO pins with automatic external mux control
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate: 6.21 kSPS/channel (161 µs settling)
Performance specifications
17.5 noise free bits at 31.25 kSPS
GENERAL DESCRIPTION
Fast settling, highly accurate, low power, 8-/16-channel,
multiplexed ADC for low bandwidth input signals with
integrated input buffers.
Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap
reference and integrated oscillator.
24 noise free bits at 1.25 SPS
INL: ±3 ppm/FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
Operates with either 3.3 V or5 V supply
Single supply
3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD
Optional split supply
AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V
Current: 1.4 mA
Eight flexible setups with configurability for output data rate,
digital filter mode, offset/gain error correction, reference selection,
buffer enables and more. This per channel configurability extends
to the output data rate used for each channel when using
sinc5 + sinc1 filter.
Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter
maximizes resolution and enhanced 50 Hz/60 Hz rejection,
with four selectable options to maximize rejection.
3-/4-wire serial digital interface (Schmitt trigger on SCLK)
Integrated diagnostic features, including CRC, register checksum,
CRC error checking
temperature sensor, crosspoint multiplexer, burnout currents,
SPI, QSPI, MICROWIRE, and DSP compatible
and GPIOs/GPOs.
Package: 40-lead 6 mm × 6 mm LFCSP
Temperature range: −40°C to +105°C
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
1.8V
LDO
CROSSPOINT
MULTIPLEXER
REFERENCE
INPUT
BUFFERS
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0/REF2–
AIN1/REF2+
AIN15
AIN16
AVDD ANALOG
INPUT
BUFFERS
Σ-Δ ADC
AVSS
I/O AND EXTERNAL
MUX CONTROL
INT
REF
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7173-8
CS
SCLK
DIN
DOUT/RDY
SYNC
ERROR
TEMPERATURE
SENSOR
AVSS
PDSW
GPIO0 GPIO1 GPO2 GPO3
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7173-8
Data Sheet
SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock = 2 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
Noise
Noise Free Resolution
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Offset Drift vs. Time3
Gain Error2
Gain Drift vs. Temperature1
Gain Drift vs. Time3
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz and 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Voltage Range
Absolute AIN Voltage Limits1
Buffers Disabled
Buffers Enabled
Analog Input Current
Buffers Enabled
Input Current
Input Current Drift
Buffers Disabled
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy1
Temperature Coefficient
0°C to +105°C
−40°C to +105°C
Reference Load Current, ILOAD
Test Conditions/Comments
Excluding sinc3 filter at 31.25 kSPS
See Table 6
See Table 6
Sinc5 + sinc1 filter (default)
31.25 kSPS, REF+ = 5 V
2.6 kSPS, REF+ = 5 V
1.25 SPS, REF+ = 5 V
2.5 V reference
5 V reference
Internal short
Internal short
25°C, AVDD1 = 5 V
Min
1.25
24
AVDD1 and AVDD2, VIN = 1 V
VIN = 0.1 V
20 SPS ODR (post filter); 50 Hz ± 1 Hz and
60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (post filter)
External clock, 20 SPS ODR (post filter)
95
120
71
85
Single cycle settling enabled (default)
AVSS − 0.05
AVSS
External clock
Internal clock (±2.5% clock)
1 kHz input
100 nF external capacitor on REFOUT to AVSS
REFOUT with respect to AVSS
TA = 25°C4
−0.1
IL −10
Typ Max
31250
Unit
SPS
Bits
17.5
18.4
24
±3
±5
±40
±350
±450
±10
±0.5
±3
±7.5
±50
±1
90
Bits
Bits
Bits
ppm/FSR
ppm/FSR
µV
nV/°C
nV/1000 hrs
ppm/FSR
ppm/FSR/°C
ppm/FSR/
1000 hrs
dB
dB
dB
90
90
±VREF
dB
dB
V
AVDD1 + 0.05 V
AVDD1 − 1.1 V
±2
±25
±6
±0.1
±0.5
−120
2.5
+0.1
3.5 8
3.5 10
+10
nA
pA/°C
µA/V
nA/V/°C
nA/V/°C
dB
V
% of V
ppm/°C
ppm/°C
mA
Rev. A | Page 4 of 64
5 Page 
AD7173-8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AIN16 1
AIN0/REF2– 2
AIN1/REF2+ 3
AIN2 4
AIN3 5
REFOUT 6
REGCAPA 7
AVSS 8
AVDD1 9
AVDD2 10
AD7173-8
TOP VIEW
(Not to Scale)
30 AIN8
29 AIN7
28 AIN6
27 AIN5
26 AIN4
25 GPO2
24 GPIO1
23 GPIO0
22 REGCAPD
21 DGND
Data Sheet
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED TO A SIMILAR PAD ON THE PCB
UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR
HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS
THROUGH THIS PAD ON THE PCB.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No. Mnemonic
Type1 Description
1 AIN16
AI Analog Input 16. Selectable through cross point mux.
2 AIN0/REF2− AI
Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between
REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through cross
point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.
3 AIN1/REF2+ AI
Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between
REF2+ and REF2−. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through cross
point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.
4 AIN2
AI Analog Input 2. Selectable through cross point mux.
5 AIN3
AI Analog Input 3. Selectable through cross point mux.
6 REFOUT
AO Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.
7 REGCAPA
AO Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.
8 AVSS
P Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.
9 AVDD1
P Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS.
10 AVDD2
P Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.
11 PDSW
AO Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register.
12 XTAL1
AI Input 1 for Crystal.
13 XTAL2/CLKIO AI/DI Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE
register (Table 25) for more information.
14 DOUT/RDY DO Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial
data output pin to access the output shift register of the ADC. The output shift register can contain data
from any of the on-chip data or control registers. The data-word/control word information is placed on the
DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY
output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready
pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the
pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to
a processor, indicating that valid data is available.
Rev. A | Page 10 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7173-8.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7173-8 | Highly Integrated Sigma-Delta ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |