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Analog Devices - Sigma-Delta ADC

Numéro de référence AD7124-8
Description Sigma-Delta ADC
Fabricant Analog Devices 
Logo Analog Devices 





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AD7124-8 fiche technique
Data Sheet
8-Channel, Low Noise, Low Power, 24-Bit,
Sigma-Delta ADC with PGA and Reference
AD7124-8
FEATURES
3 power modes
RMS noise
Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical)
Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical)
Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical)
Up to 22 noise free bits in all power modes (gain = 1)
Output data rate
Full power: 9.38 SPS to 19,200 SPS
Mid power: 2.34 SPS to 4800 SPS
Low power: 1.17 SPS to 2400 SPS
Rail-to-rail analog inputs for gains > 1
Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle
settling)
Diagnostic functions (which aid safe integrity level (SIL)
certification)
Crosspoint multiplexed analog inputs
8 differential/15 pseudo differential inputs
Programmable gain (1 to 128)
Band gap reference with 15 ppm/°C drift maximum (70 µA)
Matched programmable excitation currents
Internal clock oscillator
On-chip bias voltage generator
Low-side power switch
General-purpose outputs
Multiple filter options
Internal temperature sensor
Self and system calibration
Sensor burnout detection
Automatic channel sequencer
Per channel configuration
Power supply: 2.7 V to 3.6 V and ±1.8 V
Independent interface power supply
Power-down current: 5 µA maximum
Temperature range: −40°C to +125°C
32-lead LFCSP
3-wire or 4-wire serial interface
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
ESD: 4 kV
APPLICATIONS
Temperature measurement
Pressure measurement
Industrial process control
Instrumentation
Smart transmitters
FUNCTIONAL BLOCK DIAGRAM
AVDD REGCAPA
REFOUT
REFIN1(+) REFIN1(–)
IOVDD REGCAPD
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS/P3
AIN5/IOUT/VBIAS/P4
AIN6/IOUT/VBIAS
AIN7/IOUT/VBIAS
AIN8/IOUT/VBIAS
AIN9/IOUT/VBIAS
AIN10/IOUT/VBIAS
AIN11/IOUT/VBIAS
AIN12/IOUT/VBIAS
AIN13/IOUT/VBIAS
AIN14/IOUT/VBIAS/REFIN2(+)
AIN15/IOUT/VBIAS/REFIN2(–)
PSW
1.9V
LDO
VBIAS
CROSSPOINT
MUX
BANDGAP
REF
AVDD
BURNOUT
DETECT
PGA1
X-MUX
AVSS
AVDD
AVSS
AVSS
REFIN2(+)
REFIN2(–)
1.8V
LDO
PGA2
BUF
BUF
24-BIT
Σ-Δ ADC
REFERENCE
BUFFERS
VARIABLE
DIGITAL
FILTER
SERIAL
INTERFACE
AND
CONTROL
LOGIC
ANALOG
BUFFERS
CHANNE L
SEQUENCER
TEMPERATURE
SENSOR
DIAGNOSTICS
POWER
SWITCH
AVSS
EXCITATION
CURRENTS
GPOs
AVDD
DIAGNOSTICS
COMMUNICATIONS
POWER SUPPLY
SIGNAL CHAIN
DIGITAL
AVSS
Figure 1.
DGND
INTERNAL
CLOCK
AD7124-8
DOUT/RDY
DIN
SCLK
CS
SYNC
CLK
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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