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PDF AD7961 Data sheet ( Hoja de datos )
| Número de pieza | AD7961 | |
| Descripción | 5 MSPS PulSAR Differential ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Throughput: 5 MSPS
16-bit resolution with no missing codes
Excellent ac and dc performance
Dynamic range: 96 dB
SNR: 95.5 dB
THD: −116 dB
INL: ±0.2 LSB (typical), ±0.55 LSB (maximum)
DNL: ±0.14 LSB (typical), ±0.25 LSB (maximum)
True differential analog input voltage range: ±4.096 V or ±5 V
Low power dissipation
46.5 mW at 5 MSPS with external reference buffer
(echoed clock mode)
64.5 mW at 5 MSPS with internal reference buffer
(echoed clock mode)
39 mW at 5 MSPS with external reference buffer
(self clocked mode, CNV± in CMOS mode)
SAR architecture
No latency/pipeline delay
External reference options: 2.048 V buffered to 4.096 V (internal
reference buffer), 4.096 V, and 5 V
Serial LVDS interface
Self clocked mode
Echoed clock mode
LVDS or CMOS option for conversion control (CNV± signal)
Operating temperature range of −40°C to +85°C
32-lead, 5 mm × 5 mm LFCSP (QFN)
APPLICATIONS
Digital imaging systems
Digital X-rays
Computed tomography
IR cameras
MRI gradient control
High speed data acquisition
Spectroscopy
Test equipment
16-Bit, 5 MSPS PulSAR
Differential ADC
AD7961
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM VDD1 VDD2 VIO
IN+
IN–
AD7961
÷2 CLOCK
CAP
DAC
LOGIC
SAR
SERIAL
LVDS
EN0
EN1
EN2
EN3
CNV+, CNV–
D+, D–
DCO+, DCO–
CLK+, CLK–
GND
Figure 1.
GENERAL DESCRIPTION
The AD7961 is a 16-bit, 5 MSPS, charge redistribution successive
approximation (SAR), analog-to-digital converter (ADC). The
SAR architecture allows unmatched performance both in noise
and in linearity. The AD7961 contains a low power, high speed,
16-bit sampling ADC, an internal conversion clock, and an
internal reference buffer. On the CNV± edge, the AD7961
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and 4.096 V and between 0 V and 5 V. The reference voltage is
applied to the part externally. All conversion results are available
on a single LVDS self clocked or echoed clock serial interface.
The AD7961 is available in a 32-lead LFCSP (QFN) with
operation specified from −40°C to +85°C.
Table 1. Fast PulSAR® ADC Selection
Input Type
1 MSPS to 2 MSPS to
<2 MSPS 3 MSPS
Pseudo-
Differential,
16-Bit
AD7653
AD7667
AD7980
AD7985
AD7983
True Bipolar, AD7671
16-Bit
Differential,1
16-Bit
AD7677
AD7623
AD7621
AD7622
Differential,1
18-Bit
AD7643
AD7982
AD7641
AD7986
AD7984
5 MSPS
to 6 MSPS 10 MSPS
AD7625
AD7961
AD7960
AD7626
1 Antiphase.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7961
Data Sheet
Parameter
EXTERNAL REFERENCE
Voltage Range
Current Drain
VCM PIN
VCM Output
VCM Error
Output Impedance
LVDS I/O (ANSI-644)
Data Format
Differential Output Voltage, VOD
Common-Mode Output Voltage, VOCM
Differential Input Voltage, VID
Common-Mode Input Voltage, VICM
POWER SUPPLIES
Specified Performance
VDD1
VDD2
VIO
Operating Currents8
Static—Not Converting, Internal
Reference Buffer Disabled
VDD1
VDD2
VIO
Static—Not Converting, Internal
Reference Buffer Enabled
VDD1
VDD2
VIO
Converting: Internal Reference Buffer
Disabled
VDD1
VDD2
VIO
Converting: Internal Reference Buffer
Enabled
VDD1
VDD2
VIO
Converting: Internal Reference Buffer
Disabled
VDD1
VDD2
VIO
Snooze Mode
VDD1
VDD2
VIO
Test Conditions/Comments
REFIN pin, EN1 to EN0 = 01
REF pin, EN1 to EN0 = 106
REF pin, EN1 to EN0 = 016
5 MSPS, REF = 4.096 V
5 MSPS, REF = 5 V
RL = 100 Ω
RL = 100 Ω
Self clocked mode, CNV± in CMOS
mode9
Self clocked mode, CNV± in CMOS
mode9
Echoed clock mode, CNV± in LVDS
mode
Echoed clock mode, CNV± in LVDS
mode
Self clocked mode, CNV± in CMOS
mode9
Min Typ Max
2.048
4.096
5
1.05
1.36
1.11
1.43
−0.01
REF/2
5.1
+0.01
Serial LVDS twos complement
245 290 454
9807
1130
1375
100 650
800 1575
4.75 5 5.25
1.71 1.8 1.89
1.71 1.8 1.89
8 40
8 70
5 5.3
2.6 2.9
9 72
4.4 5.3
2 2.2
11.4 13.5
9 10.3
5.6 6
11.4 13.5
9 10.3
2 2.2
11.4 13.5
4.9 5.6
2 4.1
1 40.3
0.1 4.8
Unit
V
V
V
mA
mA
V
kΩ
mV
mV
mV
mV
V
V
V
μA
μA
mA
mA
μA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
Rev. B | Page 4 of 24
5 Page 
AD7961
250000
200000
215449
150000
100000
50000
22331
24360
00
E56F
3
E570
E571 E572 E573
CODE (HEX)
1
E574
0
E575
Figure 11. Histogram of DC Input at Code Center, REF = 4.096 V
0
–20 INPUT FREQENCY = 20kHz
SNR = 95.9dB
–40
SINAD = 95.8dB
THD = –115.5dB
SFDR = 117dB
–60
–80
–100
–120
–140
–160
–180
0
0.5 1.0 1.5 2.0 2.5
FREQUENCY (MHz)
Figure 12. 20 kHz, −0.5 dBFS Input Tone FFT, Wide View, REF = 5 V
0
–20 INPUT FREQENCY = 20kHz
SNR = 95.9dB
–40
SINAD = 95.8dB
THD = –115.5dB
SFDR = 117dB
–60
–80
–100
–120
–140
–160
–180
0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
Figure 13. 20 kHz, −0.5 dBFS Input Tone FFT, Zoomed View, REF = 5 V
Data Sheet
160000
140000
120000
136440
124393
100000
80000
60000
40000
20000
0
0
E56F
776
E570
E571
E572
535
E573
0
E574
0
E575
CODE (HEX)
Figure 14. Histogram of DC Input at Code Transition, REF = 4.096 V
0
–20 INPUT FREQENCY = 20kHz
SNR = 96.2dB
–40
SINAD = 96.1dB
THD = –121dB
SFDR = 122dB
–60
–80
–100
–120
–140
–160
–180
0
0.5 1.0 1.5 2.0 2.5
FREQUENCY (MHz)
Figure 15. 20 kHz, −6 dBFS Input Tone FFT, Wide View, REF = 5 V
0
–20 INPUT FREQENCY = 20kHz
SNR = 95.2dB
–40
SINAD = 95.1dB
THD = –110.8dB
SFDR = 113.4dB
–60
–80
–100
–120
–140
–160
–180
0
0.5 1.0 1.5 2.0
FREQUENCY (MHz)
2.5
Figure 16. 20 kHz, −0.5 dBFS Input Tone FFT, Wide View, REF = 4.096 V
Rev. B | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD7961.PDF ] | |
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