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PDF AD7923 Data sheet ( Hoja de datos )
| Número de pieza | AD7923 | |
| Descripción | 200 kSPS 12-Bit ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
AD7923
FEATURES
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB Min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPITM-/
MICROWIRETM-/DSP-compatible
Shutdown mode: 0.5 μA max
16-lead TSSOP package
Qualified for automotive applications
GENERAL DESCRIPTION
The AD7923 is a 12-bit, high speed, low power, 4-channel, suc-
cessive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS; the conversion is also initiated at this
point.
The AD7923 uses advanced design techniques to achieve very
low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
The AD7923 features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7923 is determined by the serial
clock, SCLK, frequency, since this is used as the master clock to
control the conversion. The conversion time can be as short as
800 ns with a 20 MHz SCLK.
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFIN
VIN0
•
•
•
•
•
•
•
•
•
•
•
•
•
VIN3
T/H
I/P
MUX
SEQUENCER
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7923
GND
SCLK
DOUT
DIN
CS
VDRIVE
Figure 1.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7923 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7923
dissipates just 3.6 mW of power.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with VDRIVE Function.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
of AVDD.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 μA
maximum when in full shutdown.
5. No Pipeline Delay.
The part features a SAR ADC with accurate control of the
sampling instant via a CS input and once off conversion
control.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7923
Data Sheet
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
AVDD
VDRIVE
IDD4
During Conversion
Normal Mode (Static)
Normal Mode (Operational) fSAMPLE = 200 kSPS
Using Auto Shutdown Mode fSAMPLE = 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational) fSAMPLE = 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
B Version1
VDRIVE – 0.2
0.4
±1
10
Twos Complement
Straight (Natural)
Binary
800
300
300
200
2.7/5.25
2.7/5.25
2.7
2.0
600
1.5
1.2
900
650
0.5
0.5
7.5
3.6
2.5
1.5
2.5
1.5
Unit
V min
V max
µA max
pF max
ns max
ns max
ns max
kSPS max
V min/max
V min/max
mA max
mA max
µA typ
mA max
mA max
µA typ
µA typ
µA max
µA max
mW max
mW max
µW max
µW max
µW max
µW max
Test Conditions/Comments
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
ISINK = 200 µA
Coding bit set to 0
Coding bit set to 1
16 SCLK cycles with SCLK at 20 MHz
Sinewave input
Full-scale step Input
See Serial Interface section
Digital I/Ps = 0 V or VDRIVE
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS
AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS
SCLK on or off (20 nA typ)
SCLK on or off (20 nA typ)
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
1 Temperature range: B Version: −40°C to +125°C.
2 See Terminology section.
3 Sample tested @ 25°C to ensure compliance.
4 See Power vs. Throughput Rate section.
Rev. D | Page 4 of 24
5 Page 
AD7923
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 ... 000) to
(00 ... 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 ... 110) to
(111 ... 111) from the ideal (that is, REFIN – 1 LSB) after the
offset error has been adjusted.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It defined
as the deviation of the midscale transition (all 0s to all 1s) from
the ideal VIN voltage, that is, REFIN – 1 LSB.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the last code transition (011 ... 110) to (011 ... 111)
from the ideal (that is, +REFIN – 1 LSB) after the zero-code
error has been adjusted.
Data Sheet
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the first code transition (100 ... 000) to (100 ... 001)
from the ideal (that is, −REFIN + 1 LSB) after the zero-code
error has been adjusted.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of cross-
talk between channels. It is measured by applying a full-scale
400 kHz sine wave signal to all three nonselected input channels
and determining how much that signal is attenuated in the
selected channel with a 50 kHz signal. The figure is given in the
worst-case across all four channels for the AD7923.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition, but
not the converter’s linearity. Power supply rejection is the maxi-
mum change in the full-scale transition point from a change in
power supply voltage from the nominal value.
Figure 6 shows the power supply rejection ratio vs. supply ripple
frequency for the AD7923 with no decoupling. The power sup-
ply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency, f, to the power of a 200 mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:
PSSR (dB) = 10log(Pf/PfS)
Pf is equal to the power at frequency f in the ADC output; PfS is
equal to the power at frequency fS coupled onto the ADC AVDD
supply.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
Rev. D | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD7923.PDF ] | |
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