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PDF AD805 Data sheet ( Hoja de datos )
| Número de pieza | AD805 | |
| Descripción | Data Retiming Phase-Locked Loop | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Data Retiming
Phase-Locked Loop
AD805*
FEATURES
CLOCK RECOVERY AND
155 Mbps Clock Recovery and Data Retiming
DATA RETIMING APPLICATION
Permits CCITT G.958 Type A Jitter Tolerance
Permits CCITT G.958 Type B Jitter Transfer
Random Jitter: 0.6؇ rms
Pattern Jitter: Virtually Eliminated
Jitter Peaking: Fundamentally None
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
SHIFTER
PHASE
DETECTOR
LOOP
FILTER
GAIN
Acquisition: 30 Bit Periods
Accepts NRZ Data without Preamble
Single Supply Operation: –5.2 V or +5 V
10 KH ECL Compatible
PRODUCT DESCRIPTION
The AD805 is a data retiming phase-locked loop designed for
Ouse with a Voltage-Controlled Crystal Oscillator (VCXO) to
perform clock recovery and data retiming on Nonreturn to Zero
B(NRZ) data. The circuit provides clock recovery and data
Sretiming on standard telecommunications STS-3 or STM-1
data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit
Ois used with the AD805 for specification purposes. Similar
circuit performance can be obtained using other commercially
Lavailable VCXO circuits. The AD805-VCXO circuit used for
Eclock recovery and data retiming can also be used for large
factor frequency multiplication.
TEThe AD805-VCXO circuit meets or exceeds CCITT G.958
RETIMING
MODULE
VCXO
(EXTERNAL)
AD805
RECOVERED
CLOCK
RETIMED
DATA
phase shifter, phase detector, and loop filter, act to align input
data phase errors to the stable recovered clock provided by the
VCXO. The range of the voltage-controlled phase shifter, at
least 2 Unit Intervals (UI), and the bandwidth of this loop, at
roughly 3 MHz, provide the circuit with its wideband jitter
tolerance characteristic.
The circuit can acquire lock to input data very quickly, within
44 bit periods, due to the accuracy of the VCXO and the action
of the data retiming loop. Typical integrated second-order PLLs
take at least several thousand bit periods to acquire lock. This is
due to their having a wide tuning range VCO. Decreasing the
regenerator specifications for STM-I Type A jitter tolerance and loop damping of a traditional second-order PLL shortens the
STM-1 Type B jitter transfer. The simultaneous Type A, wide- length of the circuit’s acquisition time, but at the expense of
band jitter tolerance and Type B, narrow-band jitter transfer
greater jitter peaking.
allows the use of the AD805-VCXO circuit in a regenerative
application to overcome optical line system interworking limit-
ations based on signal retiming using Type A passive tuned
device technology such as Surface-Acoustic-Wave (SAW) or
dielectric resonator filters, with Type B active devices such as
Phase-Locked Loops (PLLs).
The AD805-VCXO circuit is a second- order PLL that has no
jitter peaking. The zero used to stabilize the control loop of the
traditional second-order PLL effects the closed-loop transfer
function, causing jitter peaking in the jitter transfer function. In
the AD805-VCXO circuit, the zero needed to stabilize the loop
is implemented in the feedback path, in the voltage-controlled
The circuit VCXO provides a stable and accurate clock fre-
phase shifter. Placing the zero in the feedback path results in
quency signal with or without input data. The AD805 works
fundamentally no jitter peaking since the zero is absent from the
with the VCXO to dynamically adjust the recovered clock fre-
closed-loop transfer function.
quency to the frequency associated with the input data. This
frequency control loop tracks any low frequency component of
jitter on the input data. Since the circuit uses the VCXO for
clock recovery, it has a high Q for excellent wideband jitter at-
tenuation. The jitter transfer characteristic of the circuit is with-
in the jitter transfer requirements for a CCITT G.958 STM-1
Type B regenerator, which has a corner frequency of 30 kHz.
The AD805 overcomes the higher frequency jitter tolerance
limitations associated with traditional high Q, PLL based clock
and data recovery circuits through the use of its data retiming
loop. This loop, made up of the AD805’s voltage-controlled
*Protected by U.S. Patent No. 5,036,298
Output jitter, determined primarily by the VCXO, is a very low
0.6° rms. Jitter due to variations in input data density, pattern
jitter, is virtually eliminated in the circuit due to the AD805’s
patented phase detector.
The data retiming loop of the AD805 can be used with a passive
tuned circuit (155.52 MHz) such as a bandpass or a SAW filter
for clock recovery and data retiming. The data retiming loop
acts to servo the phase of the input data to the phase of the
recovered clock from the passive tuned circuit in this type of
application (see APPLICATIONS).
The AD805 uses 10 KH ECL levels and consumes 375 mW
from a +5 V or a –5.2 V supply. The device is specified for
REV. 0
operation over the industrial temperature range of –40°C to
+85°C and is available in a 20-pin plastic DIP.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
AD805
DIFFERENTIAL
SIGNAL
SOURCE
POWER
+
COMBINER
∑
+ 0.47µF
50Ω
+∑
50Ω
0.47µF
DATAIN
CIRCUIT
UNDER
TEST
DATAIN
– POWER
COMBINER
75Ω
1.0µF 180Ω
POWER
SPLITTER
GND
–5.2 V
100
10
1
CCITT TYPE A MASK
FILTER
NOISE
SOURCE
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
OB0
SO–5
TYPE A
LMASK
INPUT
EJITTER
TE–10
1.3 UI
0.3 UI
INPUT JITTER
CCITT TYPE B
MASK
0.1
0.1
1 10 100
FREQUENCY – kHz
Figure 5. Jitter Tolerance
1000
E-1
5E-2
3E-2
2E-2
E-2
5E-3
3E-3
2E-3
3
5E-4
3E-4
2E-4
4
80mV
20mV
INPUT
JITTER
5 ECL
–15 6
8
–20
1
10 100
JITTER FREQUENCY – kHz
1000
10
12
E-15
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S/N – dB
Figure 3. Jitter Transfer – Bandwidth
Figure 6. Bit Error Rate vs. Signal-to-Noise Ratio
0.3 UI
INPUT JITTER
–1
1.3 UI
INPUT JITTER
–3
CCITT
TYPE A MASK
INPUT JITTER
–5
1
JITTER FREQUENCY – kHz
Figure 4. Jitter Transfer – Peaking
10
VCC
2.0 IOUT
AD805
VEE = –5.2V
1.5
1.0
VCC – VOH
0.5
VOL – VEE
0
–200
0
IOUT – A
200
400
Figure 7. VCXO Control Voltage vs. Load
REV. 0
–5–
5 Page 
AD805
LARGE FACTOR FREQUENCY MULTIPLICATION —
DESKEWING ISOCHRONOUS 155.52 MBPS DATA
TO 155.52 MHZ
STREAMS
The AD805-VCXO combination can be used to multiply a
The AD805 can be used for deskewing a 155.52 Mbps data
frequency at the AD805’s DATAIN by a large integer multiple. stream to a reference 155.52 MHz clock when the clock is
This is useful for generating a 155.52 MHz bit clock from a
isochronous with the data. Figure 19 shows a diagram of an
19.44 MHz byte clock (multiplication factor of 8). The highly
AD805 in a deskewing application. The data input to the
accurate center frequency of the VCXO makes even larger
AD802-155 clock recovery circuit and the data input to the
factor frequency multiplication possible. The VCXO will not
AD805 were generated using the same 155.52 MHz clock. The
lock on a false harmonic even for large multiplication factors.
AD805 data retiming loop formed by the voltage-controlled
For example, a VCXO with center frequency accuracy of
phase shifter, the phase detector, and the loop filter act to align
100 ppm will allow frequency multiplication by a factor as large the phase of the input data to the phase of the recovered clock.
as 5000. This is because the 5000th harmonic of 31.104 kHz is This eliminates skew that can exist between two isochronous
155.52 MHz, and the 4999th and the 5001st harmonics are 200 data paths.
ppm away from the VCXO center frequency. Since the accuracy
and tuning range of the VCXO constrain its output frequency to
within 100 ppm of center frequency, the circuit will reliably pick
the 5000th harmonic.
Frequency multiplication by an odd factor is possible using the
AD805-VCXO combination. This is not obvious. Consider a
O51.84 MHz input multiplied by a factor of 3 to get to 155.52 MHz.
In this case, the edge spacing of the 51.84 MHz signal is 9.65 ns,
Bor 1-1/2 periods of the expected 155.52 MHz output. In theory,
every other edge of the 51.84 MHz at the AD805’s DATAIN is
Sinterpreted as 180° out of phase. In practice, however, the
Oinherent loop jitter dithers these edges to give +179° then –179°
out of phase measurements on alternate edges. Measurements
Lon these alternate edges cancel. The circuit phase locks to the
Eother set of alternate edges. The very low gain of the VCXO and
the narrow bandwidth of the jitter transfer function gives an
Toutput that has low jitter even though alternate input edges are
Eout of phase. When multiplying by a factor of 3, the DATAOUT
The AD805 will track ± 180° change in skew after initial locking
without bit errors. If the skew changes by more than ± 180° after
lock, it is possible to exceed the range of the voltage controlled
phase shifter. Exceeding the phase shifter range will force the
AD805 data retiming loop to reacquire to the center of the
phase shifter. During this reacquisition, it is possible to make
3000 bit errors.
CD
REFERENCE
DATA INPUT
PHASE
DETECTOR
COMPENSATING
ZERO
∑
FREQUENCY
DETECTOR
RETIMING
MODULE
LOOP
FILTER
VCO
RECOVERED
CLOCK
RETIMED
DATA
will have a repeating 110 or 100 pattern. Either pattern can
occur since either the rising or falling edges of the 51.84 MHz
AD802-155
FRAC
OUTPUT
signal at the DATAIN can be the out of phase set of alternate
edges.
Figure 18 shows the output jitter performance of an AD805-
VCXO circuit for different integer frequency multiplication
factors.
DATA
INPUT
VOLTAGE
CONTROLLED
PHASE
SHIFTER
PHASE
DETECTOR
LOOP
FILTER
GAIN
VCXO
CONTROL
OUTPUT
60
RETIMING
MODULE
BUFFERED
CLOCK
50
AD805
RETIMED
DATA
40 Figure 19. AD805 Deskewing Circuit Diagram
30
20
10
0
10
INPUT CLOCK FREQUENCY – MHz
100
Figure 19. AD805-VCXO Circuit Clock Output Jitter vs.
Integer Multiplier
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD805.PDF ] | |
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