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PDF AD8192 Data sheet ( Hoja de datos )
| Número de pieza | AD8192 | |
| Descripción | 2:1 HDMI/DVI Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8192 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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2:1 HDMI/DVI Switch with
Equalization and DDC/CEC Buffers
AD8192
FEATURES
2 inputs, 1 output HDMI/DVI links
HDMI 1.3a receive and transmit compliant
±7 kV HBM ESD on HDMI input pins
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates and beyond
Supports 25 MHz to 225 MHz pixel clocks and beyond
Fully buffered unidirectional inputs/outputs
Switchable 50 Ω on-chip input terminations with
programmable or automatic control on channel switch
Equalized inputs and pre-emphasized outputs
Low added jitter
Output disable feature for reduced power dissipation
Switched output termination for building of larger arrays
Bidirectional and cascadable DDC buffers (SDA/SCL)
DDC bus logic level translation (3.3 V, 5 V)
Bidirectional and cascadable CEC buffer with integrated
pull-up resistors (27 kΩ)
Hot plug detect pulse low on channel switch
Standards compatible: DVI, HDMI 1.3a, HDCP, I2C
Serial (I2C slave) control interface
56-lead, 8 mm × 8 mm LFCSP, RoHS-compliant package
APPLICATIONS
Front panel buffer for advanced television (HDTV) sets
Standalone HDMI switcher
Multiple input displays
Projectors
A/V receivers
Set-top boxes
GENERAL DESCRIPTION
The AD8192 is a complete HDMI™/DVI link switch featuring
equalized TMDS inputs and pre-emphasized TMDS outputs
ideal for systems with long cable runs. The TMDS outputs can
be set to a high impedance state to reduce the power dissipation
and/or allow the construction of larger arrays using the wire-
OR technique. The AD8192 includes bidirectional buffering for
the DDC bus and CEC line, with integrated pull-up resistors for
the CEC line. The AD8192 is available in a space-saving, 56-lead
LFCSP surface-mount, lead-free plastic package specified to
operate over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
I2C_SDA
I2C_SCL
I2C_ADDR
SERIAL INTERFACE
CONFIG
INTERFACE
RESET
CONTROL
LOGIC
AD8192
VTTI
AVCC
DVCC
AMUXVCC
AVEE
DVEE
VREF_AB
VREF_COM
IP_A[3:0] +
IN_A[3:0]
IP_B[3:0] +
IN_B[3:0]
4
4
EQ
4
4
SWITCH
CORE
VTTO
4 + OP[3:0]
PE 4 – ON[3:0]
VTTI
HIGH SPEED
BUFFERED
DDC_A[1:0]
DDC_B[1:0]
2
SWITCH
2 CORE
2 DDC_COM[1:0]
CEC_I/O
HPD_A
HPD_B
LOW SPEED
BUFFERED
BIDIRECTIONAL
CEC_O/I
DVEE
Figure 1.
SET-TOP BOX
TYPICAL APPLICATION
HDTV SET
HDMI
RECEIVER
DVD PLAYER
AD8192
Figure 2. Typical Application for HDTV Sets
PRODUCT HIGHLIGHTS
1. Fully HDMI 1.3a transmit and receive compliant.
2. Supports data rates up to 2.25 Gbps, enabling greater than
1080p HDMI formats with deep color (12-bit) and UXGA
(1600 × 1200) DVI resolutions.
3. Input cable equalizer enables use of long cables; more than
20 m (24 AWG) at data rates up to 2.25 Gbps.
4. Auxiliary switch isolates and buffers the DDC bus and the
CEC line, improving total system capacitance limit.
5. Hot plug detect (HPD) signal is pulsed low on link switch.
6. Manually or automatically switched input terminations.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
AD8192
Parameter
Rise Time
Fall Time
Leakage
HOT PLUG DETECT
Output Low Voltage
Symbol
Conditions/Comments
10% to 90%, CLOAD = 1500 pF, RPULLUP = 27 kΩ; or CLOAD =
7200 pF, RPULLUP = 3 kΩ
90% to 10%, CLOAD = 1500 pF, RPULLUP = 27 kΩ; or CLOAD =
7200 pF, RPULLUP = 3 kΩ
Off-leakage test conditions from HDMI Compliance Test
Specification Test ID: 8-14
VOL RPULLUP = 800 Ω to +5 V
Min
Typ Max Unit
50 100 μs
5 10 μs
1.8 μA
0.4 V
1 VREF refers to the voltage at the VREF_AB or VREF_COM pins. VREF should be at the same supply voltage as that to which the external pull-up resistors are connected.
Table 3. Power Supply and Control Logic Specifications
Parameter
Conditions/Comments
POWER SUPPLY
AVCC
Operating range (3.3 V ± 5%)
AMUXVCC
Operating range (5 V ± 10%)
VREF_AB
VREF_COM
QUIESCENT CURRENT
AVCC
Outputs disabled
AVCC
Outputs enabled, no pre-emphasis
AVCC
Outputs enabled, maximum pre-emphasis
VTTI Input termination on1
VTTO
Outputs enabled, output termination on
Output termination on, maximum pre-emphasis
DVCC
VREF_AB
VREF_COM
AMUXVCC
POWER DISSIPATION
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
I2C® AND LOGIC INPUTS2
Input High Voltage, VIH
Serial interface
Input Low Voltage, VIL
Serial interface
I2C AND LOGIC OUTPUTS
Output Low Voltage, VOL
Serial interface, IOL = +3 mA
Min
3.135
4.5
3
3
2.4
Typ Max
Unit
3.3
3.465
V
5 5.5 V
5 5.5 V
5 5.5 V
40 45
60 70
100 120
40 54
40 50
80 100
10 15
1 10
1 10
10 20
mA
mA
mA
mA
mA
mA
mA
μA
μA
mA
215 318
mW
545 765
mW
881 1200 mW
V
0.8 V
0.4 V
1 Assumes that the unselected HDMI/DVI link is deactivated through the hot plug detect line, as required by the DVI Standard Revision 1.0 and HDMI Standard Revision 1.3a.
2 The AD8192 is an I2C slave and its control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
5 Page 
AD8192
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
0.6 0.6
ALL CABLES = 24 AWG, EQ = 12dB
0.5 0.5
0.4
0.3
2.25Gbps,
EQ = 12dB
1.5Gbps,
EQ = 12dB
0.2
0.1
0.75Gbps,
EQ = 12dB
ALL CABLES = 24 AWG
0
0
5
10 15
20 25 30
35
CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
0.4
2.25Gbps, PE OFF
0.3
1.5Gbps, PE OFF
0.2
0.1
0.75Gbps, PE OFF
2.25Gbps, MAX PE
1.5Gbps, MAX PE
0.75Gbps, MAX PE
0
0 10
20 30
HDMI CABLE LENGTH (m)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50
45 DJ, EQ = 12dB
RJ, EQ = 12dB
40
35
30
25
20
15
10
5
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
1.2
1.0
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
Figure 18. Eye Height vs. Data Rate
50
DJ, EQ = 12dB
RJ, EQ = 12dB
40
30
20
10
0
3.135
3.185
3.235 3.285 3.335 3.385
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
3.435
1.2
1.0
0.8
0.6
0.4
0.2
0
3.135
3.185
3.235 3.285 3.335 3.385
SUPPLY VOLTAGE (V)
Figure 19. Eye Height vs. Supply Voltage
3.435
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD8192.PDF ] | |
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