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PDF AD9559 Data sheet ( Hoja de datos )
| Número de pieza | AD9559 | |
| Descripción | Multiservice Line Card Adaptive Clock Translator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual PLL, Quad Input, Multiservice
Line Card Adaptive Clock Translator
AD9559
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Dual digital PLL architecture with four reference inputs
(single-ended or differential)
4x2 crosspoint allows any reference input to drive either PLL
Input reference frequencies from 2 kHz to 1250 MHz
Reference validation and frequency monitoring (2 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 262 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 2 kHz
Low noise system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation
configuration
Software controlled power-down
72-lead (10 mm × 10 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9559 is a low loop bandwidth clock multiplier that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9559 generates an output clock synchronized to up to four
external input references. The digital PLL allows for reduction
of input time jitter or phase noise associated with the external
references. The digitally controlled loop and holdover circuitry
of the AD9559 continuously generates a low jitter output clock
even when all reference inputs have failed.
The AD9559 operates over an industrial temperature range of
−40°C to +85°C. If a single DPLL version of this part is needed,
refer to the AD9557.
FUNCTIONAL BLOCK DIAGRAM
AD9559
CHANNEL 0A
DIVIDER
REFERENCE
INPUT
MONITOR
AND MUX
DIGITAL
PLL 0
ANALOG
PLL 0
DIGITAL
PLL 1
ANALOG
PLL 1
CLOCK
MULTIPLIER
EEPROM
SERIAL INTERFACE
(SPI OR I2C)
÷3 TO ÷11
HF DIVIDER 0
÷3 TO ÷11
HF DIVIDER 1
STATUS AND
CONTROL PINS
CHANNEL 0B
DIVIDER
CHANNEL 1A
DIVIDER
CHANNEL 1B
DIVIDER
STABLE
SOURCE
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9559
Data Sheet
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD3 = 3.3 V; VDD = 1.8 V; TA= 25°C, unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3
VDD
Min Typ
3.135 3.30
1.71 1.80
Max Unit Test Conditions/Comments
3.465 V
1.89 V
SUPPLY CURRENT
The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1.
The test conditions for the typical (typ) supply current are at the typical supply voltage found in Table 1.
The test conditions for the minimum (min) supply current are at the minimum supply voltage found in Table 1.
Table 2.
Parameter
SUPPLY CURRENT FOR TYPICAL CONFIGURATION
Min
IVDD3
IVDD
SUPPLY CURRENT FOR ALL BLOCKS RUNNING
CONFIGURATION
IVDD3
IVDD
34
253
75
256
Typ
42
316
94
320
Max Unit Test Conditions/Comments
Typical values are for the Typical Configuration
parameter listed in Table 3
50 mA
380 mA
Maximum values are for the All Blocks Running
parameter listed in Table 3
113 mA
384 mA
Rev. C | Page 4 of 120
5 Page 
AD9559
Data Sheet
TIME DURATION OF DIGITAL FUNCTIONS
Table 9.
Parameter
Min Typ
TIME DURATION OF DIGITAL FUNCTIONS
EEPROM-to-Register Download Time
16
Register-to-EEPROM Upload Time
Power-Down Exit Time
1
Max
25
180
DIGITAL PLL (DPLL_0 AND DPLL_1)
Table 10.
Parameter
Min
DIGITAL PLL
Phase Frequency Detector (PFD) Input
Frequency Range
Loop Bandwidth
2
0.1
Typ Max
100
2000
Phase Margin
Closed Loop Peaking
45 89
<0.1
ANALOG PLL (APLL_0 AND APLL_1)
Table 11.
Parameter
Min
ANALOG PLL0
VCO Frequency Range
2940
Phase Frequency Detector (PFD) Input
Frequency Range
Loop Bandwidth
Phase Margin
ANALOG PLL1
VCO Frequency Range
Phase Frequency Detector (PFD) Input
Frequency Range
Loop Bandwidth
Phase Margin
3405
DIGITAL PLL LOCK DETECTION
Table 12.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min
10
10
HOLDOVER SPECIFICATIONS
Table 13.
Parameter
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy
Min
Typ Max
3543
180 195
240
68
4260
180 195
240
68
Typ Max
224 − 1
1
224 − 1
1
Typ Max
<0.01
Unit Test Conditions/Comments
ms Uses default EEPROM storage sequence (see Register 0x0E10
to Register 0x0E4F)
ms Uses default EEPROM storage sequence (see Register 0x0E10
to Register 0x0E4F
ms Time from power-down exit to system clock lock detect; system
clock stability timer setting should be added to calculate the
time needed for system clock stable
Unit Test Conditions/Comments
kHz
Hz
Degrees
dB
Programmable design parameter;
note that (fPFD/loop BW) ≥ 20
Programmable design parameter
Programmable design parameter; part can be programmed
for <0.1 dB peaking in accordance with Telcordia GR-253-CORE
jitter transfer
Unit Test Conditions/Comments
MHz
MHz
kHz Programmable design parameter
Degrees Programmable design parameter
MHz
MHz
kHz Programmable design parameter
Degrees Programmable design parameter
Unit Test Conditions/Comments
ps Reference-to-feedback phase difference
ps
ps Reference-to-feedback period difference
ps
Unit
ppm
Test Conditions/Comments
Excludes frequency drift of SYSCLK source; excludes frequency
drift of input reference prior to entering holdover; compliant
with GR-1244 Stratum 3
Rev. C | Page 10 of 120
11 Page | ||
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