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PDF AD9915 Data sheet ( Hoja de datos )
| Número de pieza | AD9915 | |
| Descripción | 2.5 GSPS Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
2.5 GSPS internal clock speed
Integrated 12-bit DAC
Frequency tuning resolution to 135 pHz
16-bit phase tuning resolution
12-bit amplitude scaling
Programmable modulus
Automatic linear and nonlinear frequency sweeping
capability
32-bit parallel datapath interface
8 frequency/phase offset profiles
Phase noise: −128 dBc/Hz (1 kHz offset at 978 MHz)
Wideband SFDR < −57 dBc
Serial or parallel input/output control
1.8 V/3.3 V power supplies
Software and hardware controlled power-down
88-lead LFCSP package
PLL REF CLK multiplier
Phase modulation capability
Amplitude modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulator
Fast frequency hopping
2.5 GSPS Direct Digital Synthesizer
with 12-Bit DAC
AD9915
FUNCTIONAL BLOCK DIAGRAM
AD9915
HIGH SPEED PARALLEL
MODULATION
PORT
LINEAR
SWEEP
BLOCK
2.5GSPS DDS CORE
12-BIT DAC
REF CLK
MULTIPLIER
TIMING AND CONTROL
SERIAL OR PARALLEL
DATA PORT
Figure 1.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9915
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ,
IOUT = 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O
DVDD
AVDD (3.3 V)
Min Typ Max
3.135
1.71
3.135
3.30
1.80
3.30
3.465
1.89
3.465
Unit
V
V
V
AVDD (1.8 V)
SUPPLY CURRENT
IDVDD_I/O
IDVDD
IAVDD(3.3V)
1.71 1.80 1.89
20
270
640
V
mA
mA
mA
IAVDD(1.8V)
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
148
2138 2797
mA
mW
Base DDS Power, PLL Enabled
2237 2890
mW
Linear Sweep Additional Power
Modulus Additional Power
Amplitude Scaler Additional
Power
Full Power-Down Mode
28
20
138
400 616
mW
mW
mW
mW
CMOS LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CMOS LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
REF CLK INPUT CHARACTERISTICS
2.0
2.7
DVDD_I/O V
0.8 V
±60 ±200
µA
3 pF
DVDD_I/O V
0.4 V
REF CLK Multiplier Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
REF CLK Multiplier Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
1
1.4
2
0.8 1.5
1
1.4
2
0.8 1.5
pF
kΩ
V
V p-p
pF
kΩ
V
V p-p
Test Conditions/Comments
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
See also the total power dissipation specifications
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
Manual or automatic
Using either the power-down and enable register or the
EXT_PWR_DWN pin
At VIN = 0 V and VIN = DVDD_I/O
IOH = 1 mA
IOL = 1 mA
REF CLK inputs must always be ac-coupled (both single-
ended and differential)
Single-ended, each pin
Differential
Single-ended, each pin
Differential
Rev. F | Page 4 of 47
5 Page 
AD9915
Data Sheet
Pin No.
12
18
19
20
21
22
6, 23, 73
7, 17, 24, 74, 84
16, 83
32, 56, 57
33, 35, 37, 38,
44, 46, 49, 51
34, 36, 39, 40,
43, 47, 50, 52,
53, 60
25, 26, 27
28, 29, 30, 31
41
42
45
48
54
55
58
59
61
62
63
64
65
66
Mnemonic
D8/A0
D4/SYNCIO
D3/SDO
D2/SDIO/WR
D1/SCLK/RD
D0/CS/PWD
DVDD (1.8V)
DGND
DVDD_I/O (3.3V)
AVDD (1.8V)
AGND
AVDD (3.3V)
PS0 to PS2
F0 to F3
AOUT
AOUT
DAC_BP
DAC_RSET
REF_CLK
REF_CLK
LOOP_FILTER
REF
SYNC_OUT
SYNC_IN
DRCTL
DRHOLD
DROVER
OSK
I/O1 Description
I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
I Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data.
If serial mode is invoked via F0 to F3, this pin resets the serial port.
I/O Parallel Port Pin/Serial Data Output This pin is D3 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for readback mode for serial operation.
I/O Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK,
or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial
operation. If parallel mode is enabled, this pin writes to change the values of the internal
registers.
I Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is
enabled, this pin reads back the value of the internal registers.
I Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If
serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If
parallel mode is enabled, this pin sets either 8-bit data or 16-bit data.
I Digital Core Supplies (1.8 V).
I Digital Ground.
I Digital Input/Output Supplies (3.3 V).
I Analog Core Supplies (1.8 V).
I Analog Ground.
I Analog DAC Supplies (3.3 V).
I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all input/output buffers to the corresponding registers. State changes
must be set up on the SYNC_CLK pin (Pin 82).
I Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface
is used. In addition, the function pins determine how the 32-bit parallel data-word is
partitioned for FSK, PSK, or ASK modulation mode.
O DAC Complementary Output Source. Analog output (voltage mode). Internally connected
through a 50 Ω resistor to AVDD (3.3 V).
O DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω
resistor to AVDD (3.3 V).
I DAC Bypass Pin. Provides access to the common control node of the DAC current sources.
Connecting a capacitor between this pin and ground can improve noise performance at the
DAC output.
O Analog Reference. This pin programs the DAC output full-scale reference current. Connect a
3.3 kΩ resistor to AGND.
I Complementary Reference Clock Input. Analog input.
I Reference Clock Input. Analog input.
O External PLL Loop Filter Node.
O Local PLL Reference Supply. Typically at 2.05 V.
O Digital Synchronization Output. The pin synchronizes multiple chips.
I Digital Synchronization Input. The pin synchronizes multiple chips.
I Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).
I Ramp Hold. Digital input (active high). Pauses the sweep when active.
O Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp
generator reaches the programmed upper or lower limit.
I Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude
up to the amplitude scale factor.
Rev. F | Page 10 of 47
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9915.PDF ] | |
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