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PDF AD9635 Data sheet ( Hoja de datos )
| Número de pieza | AD9635 | |
| Descripción | Serial LVDS 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual, 12-Bit, 80 MSPS/125 MSPS, Serial LVDS
1.8 V Analog-to-Digital Converter
AD9635
FEATURES
1.8 V supply operation
Low power: 115 mW per channel at 125 MSPS with scalable
power options
SNR = 71 dBFS (to Nyquist)
SFDR = 93 dBc at 70 MHz
DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging and ultrasound
Radar/LIDAR
GENERAL DESCRIPTION
The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VINA+
VINA–
VCM
VINB+
VINB–
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD9635
12-BIT PIPELINE
ADC
12
12
12-BIT PIPELINE
ADC
12
12
REFERENCE
D0A+
D0A–
D1A+
D1A–
D0B+
D0B–
D1B+
D1B–
DCO+
DCO–
FCO+
FCO–
SERIAL PORT
INTERFACE
1 TO 8
CLOCK DIVIDER
SCLK/ SDIO/ CSB
DFS PDWN
CLK+ CLK–
Figure 1.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported; the AD9635 typically consumes less
than 2 mW in the full power-down state. The ADC provides
several features designed to maximize flexibility and minimize
system cost, such as programmable output clock and data align-
ment and digital test pattern generation. The available digital
test patterns include built-in deterministic and pseudorandom
patterns, along with custom user-defined test patterns entered via
the serial port interface (SPI).
The AD9635 is available in a RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Two ADCs are contained in a small, space-
saving package.
2. Low Power. The AD9635 uses 115 mW/channel at 125 MSPS
with scalable power options.
3. Pin Compatibility with the AD9645, a 14-Bit Dual ADC.
4. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 500 MHz and supports double data
rate (DDR) operation.
5. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9635
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 139.5 MHz
fIN = 200.5 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND
AIN2 = −7.0 dBFS
fIN1 = 70.5 MHz, fIN2 = 72.5 MHz
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
POWER SUPPLY REJECTION RATIO (PSRR)4
AVDD
DRVDD
ANALOG INPUT BANDWIDTH, FULL POWER
AD9635-80
Temp Min Typ
Max
25°C
25°C
Full
25°C
25°C
71.8
71.7
70.6 71.2
69.9
68.4
25°C
25°C
Full
25°C
25°C
71.8
71.6
70.5 71.2
69.6
68.2
25°C
25°C
Full
25°C
25°C
11.6
11.6
11.4 11.5
11.3
11.0
25°C
25°C
Full 82
25°C
25°C
93
90
94
81
82
25°C
−93
25°C
−90
Full −94 −85
25°C
−81
25°C
−82
25°C
−96
25°C
−95
Full −94 −82
25°C
−95
25°C
−92
AD9635-125
Min Typ
Max
71.5
71.5
70.1 71.1
70.2
68.9
71.5
71.5
69.7 71.1
70.2
68.7
11.6
11.6
11.3 11.5
11.4
11.1
92
93
82 93
92
83
−92
−93
−93 −82
−92
−83
−95
−95
−94 −82
−93
−89
25°C
−92
25°C
−97
25°C
−97
25°C
44
25°C
59
25°C
650
−92
−97
−97
43
66
650
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3 Overrange condition is specified with 3 dB of the full-scale input range.
4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitude of the spur voltage over the amplitude of the pin voltage, expressed in decibels (dB).
Rev. B | Page 4 of 36
5 Page 
AD9635
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs to AGND
(D0x±, D1x±, DCO+, DCO−,
FCO+, FCO−)
CLK+, CLK− to AGND
VINx+, VINx− to AGND
SCLK/DFS, SDIO/PDWN, CSB to AGND
RBIAS to AGND
VREF to AGND
VCM to AGND
Environmental
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−40°C to +85°C
150°C
300°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
The exposed paddle is the only ground connection on the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec)
θJA1, 2
32-Lead LFCSP, 0
5 mm × 5 mm 1.0
37.1
32.4
2.5 29.1
θJC1, 3
3.1
θJB1, 4
20.7
ΨJT1, 2
0.3
0.5
0.8
1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Unit
°C/W
°C/W
°C/W
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces the θJA.
ESD CAUTION
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9635.PDF ] | |
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