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PDF AD9634 Data sheet ( Hoja de datos )
| Número de pieza | AD9634 | |
| Descripción | 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9634
FEATURES
SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9634 is designed to
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+
VIN–
VCM
PIPELINE 12
12-BIT
ADC
PARALLEL
AD9634
DDR LVDS
AND
DRIVERS
REFERENCE
SERIAL PORT
1-TO-8
CLOCK DIVIDER
D0±./D1±
.
.
D10±/D11±
DCO±
OR±
SCLK SDIO
CSB
CLK+ CLK–
Figure 1.
Programming for setup and control is accomplished using a
3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product
is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9642, allowing a simple
migration up to 14 bits, and with the AD6672.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9634
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
AD9634-170
AD9634-210
AD9634-250
Temperature Min Typ Max Min Typ Max Min Typ Max Unit
25°C 70.3 70.2 70.1 dBFS
25°C 70.1 70.1 70.0 dBFS
Full 69.1
68.8
dBFS
25°C 69.9 70.0 69.9 dBFS
25°C 69.5 69.6 69.7 dBFS
Full 67.8 dBFS
25°C 69.2 69.2 69.3 dBFS
25°C 69.4 69.2 69.2 dBFS
25°C 69.2 69.1 69.0 dBFS
Full 68.1
67.8
dBFS
25°C 68.9 69.1 69.0 dBFS
25°C 68.5 68.7 68.7 dBFS
Full 66.7 dBFS
25°C 68.3 68.3 68.4 dBFS
25°C 11.2 11.2 11.2 Bits
25°C 11.2 11.2 11.2 Bits
25°C 11.1 11.2 11.2 Bits
25°C 11.1 11.1 11.1 Bits
25°C 11.0 11.0 11.1 Bits
25°C −96 −96 −90 dBc
25°C −95 −92 −89 dBc
Full
−83 −80
dBc
25°C −97 −94 −91 dBc
25°C −86 −95 −87 dBc
Full −80 dBc
25°C −84 −84 −93 dBc
25°C 96
25°C 95
Full 83
25°C 97
25°C 86
Full
25°C 84
96
92
80
94
95
84
90
89
91
87
80
93
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C −98 −96 −95 dBc
25°C −97 −95 −95 dBc
Full
−87 −83
dBc
25°C −98 −97 −96 dBc
25°C −95 −95 −94 dBc
Full −81 dBc
25°C −96 −95 −94 dBc
Rev. B | Page 4 of 30
5 Page 
AD9634
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLK+ 1
CLK– 2
AVDD 3
OR– 4
OR+ 5
D0–/D1– (LSB) 6
D0+/D1+ (LSB) 7
DRVDD 8
AD9634
TOP VIEW
(Not to Scale)
24 CSB
23 SCLK
22 SDIO
21 DCO+
20 DCO–
19 D10+/D11+ (MSB)
18 D10–/D11– (MSB)
17 DRVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
ADC Power Supplies
8, 17 DRVDD
3, 27, 28, 31, 32
AVDD
0 AGND, Exposed
Paddle
Type
Supply
Supply
Ground
25
ADC Analog
30
29
26
DNC
VIN+
VIN−
VCM
Input
Input
Output
1
2
Digital Outputs
5
4
7
6
10
9
12
11
14
13
16
15
19
18
21
20
CLK+
CLK−
Input
Input
OR+
OR−
D0+/D1+ (LSB)
D0−/D1− (LSB)
D2+/D3+
D2−/D3−
D4+/D5+
D4−/D5−
D6+/D7+
D6−/D7−
D8+/D9+
D8−/D9−
D10+/D11+ (MSB)
D10−/ D11− (MSB)
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
Do No Connect. Do not connect to this pin.
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Overrange—True.
Overrange—Complement.
DDR LVDS Output Data 0/Data 1—True (LSB).
DDR LVDS Output Data 0/Data 1—Complement (LSB).
DDR LVDS Output Data 2/Data 3—True.
DDR LVDS Output Data 2/Data 3—Complement.
DDR LVDS Output Data 4/Data 5—True.
DDR LVDS Output Data 4/Data 5—Complement.
DDR LVDS Output Data 6/Data 7—True.
DDR LVDS Output Data 6/Data 7—Complement.
DDR LVDS Output Data 8/Data 9—True.
DDR LVDS Output Data 8/Data 9—Complement.
DDR LVDS Output Data 10/Data 11—True (MSB).
DDR LVDS Output Data 10/Data 11—Complement (MSB).
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
Rev. B | Page 10 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9634.PDF ] | |
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