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PDF AD9691 Data sheet ( Hoja de datos )
| Número de pieza | AD9691 | |
| Descripción | Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 1.25 GSPS JESD204B,
Dual Analog-to-Digital Converter
AD9691
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
1.9 W total power per channel (default settings)
SFDR = 77 dBFS at 340 MHz
SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS)
Noise density = −152.6 dBFS/Hz
1.25 V, 2.50 V, and 3.3 V dc supply operation
No missing codes
1.58 V p-p differential full scale input voltage
Flexible termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
1.5 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detection bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 cascaded half-band filters
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Timestamp feature
Small signal dither
APPLICATIONS
Communications (wideband receivers and digital predistortion)
Instrumentation (spectrum analyzers, network analyzers,
integrated RF test solutions)
DOCSIS 3.x CMTS upstream receive paths
High speed data acquisition systems
GENERAL DESCRIPTION
The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter
(ADC). The device has an on-chip buffer and sample-and-hold
circuit designed for low power, small size, and ease of use. The
device is designed for sampling wide bandwidth analog signals
of up to 1.5 GHz.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
Each ADC data output is internally connected to two digital
downconverters (DDCs). Each DDC consists of four cascaded
signal processing stages: a 12-bit frequency translator (NCO)
and four half-band decimation filters.
In addition to the DDC blocks, the AD9691 has a programmable
threshold detector that allows monitoring of the incoming
signal power using the fast detect output bits of the ADC. Because
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD_SR DVDD DRVDD SPIVDD
(1.25V) (2.50V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
BUFFER
ADC
CORE
14
FD_A
FD_B
VIN+B
VIN–B
SIGNAL
MONITOR
ADC
CORE
BUFFER
14
V_1P0
AD9691
CLK+
CLK–
CLOCK
GENERATION
÷2
÷4
÷8
DIGITAL
DOWN-
CONVERTER
DIGITAL
DOWN-
CONVERTER
SERDOUT0±
8
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
CONTROL
REGISTERS
FAST
DETECT
SIGNAL
MONITOR JESD204B
SUBCLASS 1
CONTROL
SPI CONTROL
SYNCINB±
SYSREF±
PDWN/
STBY
AGND DRGND DGND
SDIO SCLK CSB
Figure 1.
this threshold indicator has low latency, the user can quickly
turn down the system gain to avoid an overrange condition at
the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, four- or eight-lane
configurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± input pins.
The AD9691 is available in a Pb-free, 88-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Low power consumption analog core, 14-bit, 1.25 GSPS
dual ADC with 1.9 W per channel.
2. Wide full power bandwidth supports intermediate
frequency (IF) sampling of signals up to 1.5 GHz.
3. Buffered inputs with programmable input termination
eases filter design and implementation.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 12 mm × 12 mm, 88-lead LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9691
Data Sheet
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings,
TA = 25°C, unless otherwise noted.
Table 2.
Parameter1
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 750 MHz
fIN = 985 MHz
fIN = 1205 MHz
fIN = 1600 MHz
fIN = 1950 MHz
SNR AND DISTORTION RATIO (SINAD)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 750 MHz
fIN = 985 MHz
fIN = 1205 MHz
fIN = 1600 MHz
fIN = 1950 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 750 MHz
fIN = 985 MHz
fIN = 1205 MHz
fIN = 1600 MHz
fIN = 1950 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 750 MHz
fIN = 985 MHz
fIN = 1205 MHz
fIN = 1600 MHz
fIN = 1950 MHz
Temperature
Full
Full
Min
25°C
Full 60.8
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full 60.5
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full 9.7
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full 72
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Typ
1.58
−152.6
Max
64.6
64.2
63.4
62.9
61.7
59.7
58.3
56.5
55.1
64.5
64.0
63.0
62.3
61.3
59.4
57.5
55.8
54.7
10.4
10.3
10.2
10.1
9.9
9.6
9.2
9.0
8.8
87
79
77
72
73
72
66
66
69
Unit
V p-p
dBFS/Hz
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Rev. 0 | Page 4 of 72
5 Page 
AD9691
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
AVDD1 1
AVDD1 2
AVDD2 3
AVDD3 4
VIN–A 5
VIN+A 6
AVDD3 7
AVDD2 8
AVDD2 9
AVDD2 10
AVDD2 11
V_1P0 12
SPIVDD 13
PWDN/STBY 14
DVDD 15
DGND 16
DNC 17
DNC 18
DNC 19
DNC 20
FD_A 21
DNC 22
AD9691
TOP VIEW
(Not to Scale)
66 AVDD1
65 AVDD1
64 AVDD2
63 AVDD3
62 VIN–B
61 VIN+B
60 AVDD3
59 AVDD2
58 AVDD2
57 AVDD2
56 SPIVDD
55 CSB
54 SCLK
53 SDIO
52 DVDD
51 DGND
50 DNC
49 DNC
48 DNC
47 DNC
46 FD_B
45 DNC
NOTES
1. DNC = DO NOT CONNECT. THESE PINS MUST BE LEFT UNCONNECTED.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFERENCE FOR AVDDX.
THE EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND.
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Power Supplies
0 EPAD
1, 2, 65, 66, 68, 72, 76, 83, 87
3, 8, 9, 10, 11, 57, 58, 59,
64, 69, 71, 84, 86
4, 7, 60, 63
13, 56
15, 52
16, 51
23, 44
24, 43
77, 81
78
Analog
5, 6
12
AVDD1
AVDD2
AVDD3
SPIVDD
DVDD
DGND
DRGND
DRVDD
AGND 1
AVDD1_SR1
VIN−A, VIN+A
V_1P0
61, 62
74, 75
VIN+B, VIN−B
CLK+, CLK−
Type
Ground
Supply
Supply
Supply
Supply
Supply
Ground
Ground
Supply
Ground
Supply
Input
Input/DNC
Input
Input
Description
Exposed Pad. The exposed thermal pad on the bottom of the
package provides the ground reference for AVDDx. The
exposed thermal pad must be connected to AGND.
Analog Power Supply (1.25 V Nominal).
Analog Power Supply (2.50 V Nominal).
Analog Power Supply (3.3 V Nominal).
Digital Power Supply for SPI (1.8 V to 3.3 V).
Digital Power Supply (1.25 V Nominal).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Digital Driver Power Supply (1.25 V Nominal).
Ground Reference for SYSREF±.
Analog Power Supply for SYSREF± (1.25 V Nominal).
ADC A Analog Input Complement/True.
1.0 V Reference Voltage Input/Do Not Connect. This pin is
configurable through the SPI as a no connect or as an input.
Do not connect this pin if using the internal reference. This pin
requires a 1.0 V reference voltage input if using an external
voltage reference source.
ADC B Analog Input True/Complement.
Clock Input True/Complement.
Rev. 0 | Page 10 of 72
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9691.PDF ] | |
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