PDF AD9681 Data sheet ( Hoja de datos )

Número de pieza	AD9681
Descripción	1.8 V Analog-to-Digital Converter
Fabricantes	Analog Devices
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Data Sheet Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter AD9681 FEATURES Low power 8 ADC channels integrated into 1 package 110 mW per channel at 125 MSPS with scalable power options SNR: 74 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist) DNL: ±0.8 LSB (typical); INL: ±1.2 LSB (typical) Crosstalk, worst adjacent channel, 70 MHz, −1 dBFS: −83 dB typical Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 650 MHz full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Power-down and standby modes APPLICATIONS Medical imaging Communications receivers Multichannel data acquisition GENERAL DESCRIPTION The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The AD9681 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO±1, DCO±2) for capturing data on the output and frame clock outputs (FCO±1, FCO±2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD AD9681 VIN+A1 VIN–A1 VIN+A2 VIN–A2 14 PIPELINE ADC 14 PIPELINE ADC DIGITAL SERIALIZER DIGITAL SERIALIZER SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS D0+A1 D0–A1 D1+A1 D1–A1 D0+A2 D0–A2 D1+A2 D1–A2 VIN+D1 VIN–D1 VIN+D2 VIN–D2 VREF SENSE VCM1, VCM2 GND 14 PIPELINE ADC 14 PIPELINE ADC DIGITAL SERIALIZER DIGITAL SERIALIZER REF SELECT 1V SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL PORT INTERFACE CLOCK MANAGEMENT D0+D1 D0–D1 D1+D1 D1–D1 D0+D2 D0–D2 D1+D2 D1–D2 FCO+1, FCO+2 FCO–1, FCO–2 DCO+1, DCO+2 DCO–1, DCO–2 Figure 1. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9681 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Small Footprint. Eight ADCs are contained in a small, 10 mm × 10 mm package. 2. Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options. 3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation. 4. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9681 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD IDRVDD (ANSI-644 Mode) IDRVDD (Reduced Range Mode) TOTAL POWER CONSUMPTION Total Power Dissipation (Eight Channels, Including Output Drivers ANSI-644 Mode) Total Power Dissipation (Eight Channels, Including Output Drivers Reduced Range Mode) Power-Down Dissipation Standby Dissipation2 Temp Full Full Full Full Full Full Full Full Full Full 25°C Full 25°C Full Full Full Full Full Full Full Full 25°C Full 25°C 25°C 25°C Min 14 −0.23 0 −8.0 0 −0.92 −4.0 0.98 0.5 1.7 1.7 Typ Max Guaranteed +0.21 0.24 −3.1 1.8 ±0.8 ±1.2 +0.62 0.7 +1.7 6.0 +1.75 +4.0 −4 38 1.0 1.02 3 7.5 0.99 2 0.9 1.3 5.2 3.5 1.8 1.9 1.8 1.9 368 423 120 126 90 879 988 825 2 485 Unit Bits % FSR % FSR % FSR % FSR LSB LSB ppm/°C ppm/°C V mV kΩ LSB rms V p-p V kΩ pF V V mA mA mA mW mW mW mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for information about how these tests were completed. 2 Controlled via the SPI. Rev. C \| Page 4 of 40 5 Page AD9681 VIN±x1, VIN±x2 CLK– CLK+ DDR SDR DCO–1, DCO–2 DCO+1, DCO+2 DCO–1, DCO–2 DCO+1, DCO+2 FCO–1, FCO–2 BITWISE MODE FCO+1, FCO+2 D0–A1 D0+A1 D1–A1 D1+A1 FCO–1, FCO–2 BYTEWISE MODE FCO+1, FCO+2 D0–A1 D0+A1 D1–A1 D1+A1 N–1 tA tEH tCPD N tEL Data Sheet N+1 tFCO tFRAME D10 N – 17 tPD D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 tDATA D10 D08 N – 16 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 MSB N – 16 D09 N – 16 tLD D07 D05 N – 16 N – 16 D03 N – 16 D01 N – 16 D05 D04 D03 D02 D01 LSB D05 D04 D03 D02 D01 LSB N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 MSB D10 D09 D08 D07 D06 MSB D10 D09 D08 D07 D06 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 16 Figure 6. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode VIN±x1, VIN±x2 CLK– CLK+ DCO–1, DCO–2 DCO+1, DCO+2 FCO–1, FCO–2 FCO+1, FCO+2 D0–x/D1–x D0+x/D1+x N–1 tA tEH tCPD N tEL tFCO tFRAME tPD tDATA MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 0 0 MSB D14 D13 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 Figure 7. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode (See Table 8 for One-Lane Channel Assignments) Rev. C \| Page 10 of 40 11 Page

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