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PDF AD9680 Data sheet ( Hoja de datos )
| Número de pieza | AD9680 | |
| Descripción | Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS
JESD204B, Dual Analog-to-Digital Converter
AD9680
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range: 1.46 V p-p to 1.94 V p-p
AD9680-1250: 1.58 V p-p nominal
AD9680-1000 and AD9680-820: 1.70 V p-p nominal
AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
FD_A
FD_B
VIN+B
VIN–B
V_1P0
CLK+
CLK–
BUFFER
ADC
CORE 14
SIGNAL
MONITOR
DDC
4
14
ADC
CORE
BUFFER
DDC
CONTROL
REGISTERS
FAST
DETECT
CLOCK
GENERATION
SIGNAL
MONITOR
JESD204B
SUBCLASS 1
CONTROL
÷2 SPI CONTROL
÷4
÷8 AD9680
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
SYSREF±
PDWN/
STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
2. Buffered inputs with programmable input termination eases
filter design and implementation.
3. Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-lead LFCSP.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9680
GENERAL DESCRIPTION
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/
500 MSPS analog-to-digital converter (ADC). The device has
an on-chip buffer and sample-and-hold circuit designed for low
power, small size, and ease of use. This device is designed for
sampling wide bandwidth analog signals of up to 2 GHz. The
AD9680 is optimized for wide input bandwidth, high sampling
rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog input and clock signals are differential inputs. Each
ADC data output is internally connected to two digital down-
converters (DDCs). Each DDC consists of up to five cascaded
signal processing stages: a 12-bit frequency translator (NCO),
and four half-band decimation filters. The DDCs are bypassed
by default.
In addition to the DDC blocks, the AD9680 has several
functions that simplify the automatic gain control (AGC)
Data Sheet
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane
configurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The AD9680 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
Rev. C | Page 4 of 97
5 Page 
AD9680
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min Typ Max Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3
tSU_SR
Device clock to SYSREF+ setup time
117 ps
tH_SR Device clock to SYSREF+ hold time
−96 ps
SPI TIMING REQUIREMENTS
See Figure 4
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK Period of the SCLK
40 ns
tS
Setup time between CSB and SCLK
2 ns
tH
Hold time between CSB and SCLK
2 ns
tHIGH
Minimum period that SCLK must be in a logic high state
10
ns
tLOW
Minimum period that SCLK must be in a logic low state
10
ns
tACCESS
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
6 10 ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in Figure 4)
10
ns
Timing Diagrams
APERTURE
DELAY
ANALOG
INPUT
SIGNAL
N – 55
N – 54
N – 53
N – 52
N – 51
SAMPLE N
N–1
N+1
CLK–
CLK+
CLK–
CLK+
SERDOUT0–
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
ABCDE FGH I J ABCDE FGH I J ABCDE FGH I J
CONVERTER0 MSB
ABCDE FGH I J ABCDE FGH I J ABCDE FGH I J
CONVERTER0 LSB
ABCDE FGH I J ABCDE FGH I J ABCDE FGH I J
CONVERTER1 MSB
ABCDE FGH I J ABCDE FGH I J ABCDE FGH I J
SAMPLE N – 55
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
SAMPLE N – 54
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
SAMPLE N – 53
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)
CONVERTER1 LSB
Rev. C | Page 10 of 97
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9680.PDF ] | |
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