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PDF LC72121MA Data sheet ( Hoja de datos )
| Número de pieza | LC72121MA | |
| Descripción | PLL Frequency Synthesizers | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA2009
LC72121MA
CMOS IC
PLL Frequency Synthesizers
for Electronic Tuning
http://onsemi.com
Overview
The LC72121MA are high input sensitivity (20mVrms at 130MHz) PLL frequency synthesizers for 3V systems.
These ICs are serial data (CCB) compatible with the LC72131K/KMA, and feature the improved input sensitivity and
lower spurious radiation (provided by a redesigned ground system) required in high-performance AM/FM tuners.
Features
• High-speed programmable divider
• FMIN: 10 to 160MHz ·············· Pulse swallower technique (With built-in divide-by-2 prescaler)
• AMIN: 2 to 40MHz ················ Pulse swallower technique
0.5 to 10MHz ·············· Direct division technique
• IF counter
• IFIN: 0.4 to 15MHz ················ For AM and FM IF counting
• Reference frequency
• One of 12 reference frequencies can be selected (using a 4.5 or 7.2MHz crystal element)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100kHz
• Phase comparator
• Supports dead zone control. • Built-in unlocked state detection circuit • Built-in deadlock clear circuit
• An MOS transistor for an active low-pass filter is built in.
• I/O ports
• Output-only ports: 4 pins
• I/O ports: 2 pins
• Supports the output of a clock time base signal.
• Serial data I/O
• Support CCB format communication with the system controller.
• Operating ranges
• Supply voltage: 2.7 to 3.6V • Operating temperature: -40 to +85°C
• Package
• MFP24SJ
• CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
• CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
June, 2013
30712HKPC 20120124-S00002 No.A2009-1/24
1 page  
Block Diagram
VSSX
XIN
XOUT
FMIN
1/2
LC72121MA
REFERENCE
DIVIDER
SWALLOW COUNTER
1/16,1/17 4bits
PHASE DETECTOR
CHARGE PUMP
UNLOCK
DETECTOR
AMIN
CE
DI
CL
DO
VDD
VSSd
12bits PROGRAMMABLE
DIVIDER
CCB
I/F
POWER
ON
RESET
DATA SHIFT REGISTER
LATCH
UNIVERSAL
COUNTER
BO1 BO2 BO3 BO4
IO1 IO2
PD
AIN
AOUT
VSSa
IFIN
No.A2009-5/24
5 Page 
LC72121MA
Continued from preceding page.
No. Control block/data
DO pin control data
(6) DOC0
DOC1
DOC2
Unlocked state
(7) detection data
UL0, UL1
Phase comparator
(8) control data
DZ0, DZ1
(9)
Clock time base
TBC
Charge pump
(10) control data
DLC
IF counter control
(11) data
IFS
Test data
(12) TEST0 to 2
(13) DNC
Function
• Determines the DO pin output.
DOC2 DOC1 DOC0
DO pin state
000
001
010
011
Open
Low when the PLL is unlocked
end-UC *1
Open
100
101
110
111
Open
The IO1 pin state *2
The IO2 pin state *2
Open
The open state is selected after a power on reset.
*1. end-UC: IF counter measurement end check
DO pin
(1) Count start
(2) Count end
CE:high
(1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin
automatically goes to the open state.
(2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing
applications to test for the completion of the count period.
(3)The DO pin is set to the open state by performing a serial data input or output operation (when
the CE pin is set high).
*2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port.
Note) During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes
to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data
output period (the period that CE is high in OUT mode) the DO pin state reflects the internal
DO serial data in synchronization with the CL clock, regardless of the DO pin control data
(DOC0 to DOC2).
• Selects the width of the phase error (φE) detected for PLL lock state discrimination. The state is
taken to be unlocked if a phase error in excess of the detection width occurs.
UL1 UL0
φE detection width
Detection output
00
Stop
Open
01
0
φE is output directly
10
±0.55μs
φE is extended by 1 to 2ms
11
±1.11μs
↑
* When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0.
• Controls the phase comparator dead zone
DZ1 DZ0
Dead zone mode
00
DZA
01
DZB
10
DZC
11
DZD
Dead zone width: DZA < DZB < DZC < DZD
• Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from
the BO1 pin. (The BO1 data will be ignored.)
• Forcibly controls the charge pump output.
DLC Charge pump output
0 Normal operation
1 Forced Low
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being
stopped, applications can get out of the deadlocked state by setting the charge pump output to
low and setting Vtune to VCC. (Deadlock clear circuit)
• This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity
mode, in which the sensitivity is reduced by about 10 to 30mV rms.
* See the “IF Counter Operation” section for details.
• Test data
TEST0
TEST1 All these bits must be set to 0.
TEST2
All these bits are set to 0 after a power on reset.
• This bit must be set to 0.
Related data
UL0, UL1
CTE
IOC1
IOC2
DOC0
DOC1
DOC2
BO1
No.A2009-11/24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LC72121MA.PDF ] | |
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