|
|
PDF AD9245 Data sheet ( Hoja de datos )
| Número de pieza | AD9245 | |
| Descripción | 3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9245 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converter
AD9245
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9245
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
16
3
REF
SELECT
CORRECTION LOGIC
14
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OTR
D13 (MSB)
D0 (LSB)
AGND
CLK PDWN MODE DGND
Figure 1.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9245
Data Sheet
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error1
Gain Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error1
Gain Error
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
Low Frequency Input4
Standby Power5
AD9245BCP-80
Min Typ
Max
14
Guaranteed
±0.30
±0.28
±0.70
±0.5
±1.4
±1.2
±4.16
±1.0
±5.15
±10
±12
±17
±3 ±34
±2
±6
±1
1.86
1.17
1
2
7
7
2.7 3.0
2.25 2.5
122
9
±0.01
366
1.0
3.6
3.6
138
Unit
Bits
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
V
V
mA
mA
% FSR
mW
mW
1 With a 1.0 V internal reference.
2 Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.
4 Measured at ac specification conditions without output drivers.
5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).
Rev. E | Page 4 of 32
5 Page 
AD9245
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Total Harmonic Distortion (THD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Data Sheet
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
ENOB
=
(SINAD −
6.02
1.76)
Signal-to-Noise Ratio (SNR)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the Logic 0 state. At a given clock rate,
these specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
1 AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. E | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9245.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9240 | Monolithic A/D Converter | Analog Devices |
| AD9241 | Complete 14-Bit/ 1.25 MSPS Monolithic A/D Converter | Analog Devices |
| AD9243 | Monolithic A/D Converter | Analog Devices |
| AD9244 | 14-Bit 40/65 MSPS Monolithic A/D Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |